One-time programmable (OTP) memory controller with a control circuit configured to assert a pre-load start signal and a pre-load end signal, related processing system, integrated circuit and method
US-12353880-B2 · Jul 8, 2025 · US
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Guarnaccia Giuseppe patents
Guarnaccia Giuseppe is listed as an inventor on 22 patents in our database. Major assignees and classification codes are summarized below.
| Metric | Value |
|---|---|
| Inventor | Guarnaccia Giuseppe |
| Total patents | 22 |
| First publication | Apr 23, 2015 |
| Latest publication | Jul 8, 2025 |
Notable patents
Publications ranked by popularity score, then publication date.
Register shielding in semiconductor devices
US-12307002-B2 · May 20, 2025 · US
One-time programmable memory controller, related processing system, integrated circuit and method
US-2023409320-A1 · Dec 21, 2023 · US
Register shielding in semiconductor devices
US-2023055842-A1 · Feb 23, 2023 · US
Cryptography method and circuit, corresponding device
US-11456857-B2 · Sep 27, 2022 · US
Processing system, related integrated circuit and method
US-11281807-B2 · Mar 22, 2022 · US
Decryption method and circuit, corresponding device
US-11042655-B2 · Jun 22, 2021 · US
Binary-to-gray conversion circuit, related FIFO memory, integrated circuit and method
US-10635394-B2 · Apr 28, 2020 · US
Method and apparatus for supporting the use of interleaved memory regions
US-10540277-B2 · Jan 21, 2020 · US
Cryptography method and circuit, corresponding device
US-2019386816-A1 · Dec 19, 2019 · US
Recent patents
Latest publications not already listed above.
Processing System, Related Integrated Circuit and Method
US-2019354726-A1 · Nov 21, 2019 · US
Method and apparatus for use with different memory maps
US-10419432-B2 · Sep 17, 2019 · US
Decryption method and circuit, corresponding device
US-2019278926-A1 · Sep 12, 2019 · US
Binary-to-gray conversion circuit, related fifo memory, integrated circuit and method
US-2019265947-A1 · Aug 29, 2019 · US
Bi-synchronous electronic device with burst indicator and related methods
US-9727306-B2 · Aug 8, 2017 · US
Method and apparatus for supporting reprogramming or reconfiguring
US-9660936-B2 · May 23, 2017 · US
Method and apparatus for supporting the use of interleaved memory regions
US-2016246714-A1 · Aug 25, 2016 · US
Method and apparatus for use with different memory maps
US-2016226878-A1 · Aug 4, 2016 · US
Bi-synchronous electronic device and FIFO memory circuit with jump candidates and related methods
US-9311975-B1 · Apr 12, 2016 · US
Bi-synchronous electronic device and fifo memory circuit with jump candidates and related methods
US-2016099032-A1 · Apr 7, 2016 · US
Bi-synchronous electronic device with burst indicator and related methods
US-2016099031-A1 · Apr 7, 2016 · US
Method and apparatus for supporting reprogramming or reconfiguring
US-2015109916-A1 · Apr 23, 2015 · US
Major assignees
Companies most often associated with this inventor's publications.
| Assignee | Patents |
|---|---|
| St Microelectronics Srl | 22 |
| St Microelectronics Grenoble 2 | 5 |
| St Microelectronics Sa | 2 |
| Stmicroelectronics (Grenoble2) Sas | 2 |
| Stmicroelectronics Grenoble2 Sas | 1 |
Top CPC classifications
Most common classification codes across this inventor's patents.
| CPC | Patents |
|---|---|
| G06F2205/102 | 6 |
| G06F21/85 | 6 |
| G06F21/74 | 6 |
| G11C7/222 | 5 |
| G06F5/10 | 4 |