One-time programmable (OTP) memory controller with a control circuit configured to assert a pre-load start signal and a pre-load end signal, related processing system, integrated circuit and method

Patent metadata

Field	Value
Publication number	US-12353880-B2
Application number	US-202318325519-A
Country	US
Kind code	B2
Filing date	May 30, 2023
Priority date	Jun 16, 2022
Publication date	Jul 8, 2025
Grant date	Jul 8, 2025

Abstract

In an embodiment a One-Time Programmable (OTP) memory controller includes a data register, a given number K of shadow-registers, wherein the number K is smaller than a given number N of memory slots of an OTP memory area, a communication interface configured to receive a read request requesting the data of a given memory slot and a control circuit configured to receive a preload start signal and a shadow-register preload enable signal, wherein the control circuit is configured to manage a preload phase and a data-read phase.

First claim

What is claimed is:

1. A One-Time Programmable (OTP) memory controller comprising:
a data register;
a given number K of shadow-registers, wherein the number K is smaller than a given number N of memory slots of an OTP memory area;
a communication interface configured to receive a read request requesting data of a memory slot; and
a control circuit configured to receive a preload start signal and a shadow-register preload enable signal, wherein the control circuit is configured to manage a preload phase and a data-read phase,
wherein, in response to the preload start signal, the control circuit is configured to perform the preload phase by:
determining a mapping between the given number K of shadow-registers and the given number N of memory slots,
determining, for each of the given number K of shadow-registers, whether a shadow-register is preloadable as a function of the shadow-register preload enable signal,
in response to determining that the shadow-register is preloadable, transferring the data from the memory slot mapped to the shadow-register, the respective memory slot being mapped to the shadow-register, and
once the shadow-register is preloaded based on the shadow-register preload enable signal, asserting a preload end signal and starting the data-read phase, and

wherein the control circuit is configured to perform the data-read phase by:
selecting a memory location indicated in the read request,
determining whether the selected memory location is mapped to the shadow-register,
in response to determining that the selected memory location is mapped to the shadow-register, selecting the shadow-register mapped to the selected memory location and determining whether the selected shadow-register has been pre-loaded,
in response to determining that the selected shadow-register has been pre-loaded, transmitting the data stored in the selected shadow-register via the communication interface,
in response to determining that the selected shadow-register has not been pre-loaded, transferring the data from a selected memory slot to the selected shadow-register and then transmitting the data stored in the selected shadow-register via the communication interface, and
in response to determining that the selected memory location is not mapped to the shadow-register, transferring the data from the selected memory slot to the data register and then transmitting the data stored in the data register via the communication interface.

2. The OTP memory controller according to claim 1 , wherein the control circuit is configured to:
receive a shadow-register mapping signal; and
determine the mapping between the given number K of shadow-registers and the given number N of memory slots as a function of the shadow-register mapping signal.

3. The OTP memory controller according to claim 1 , wherein the shadow-register preload enable signal comprises a given number N of bits, and wherein each bit indicates whether a respective memory slot is preloadable.

4. The OTP memory controller according to claim 1 , wherein the shadow-register preload enable signal comprises a given number K of bits, and wherein each bit indicates whether a respective shadow register is preloadable.

5. The OTP memory controller according to claim 1 , wherein the control circuit is configured to perform a data-write phase by:
receiving a write request via the communication interface and selecting a respective memory location indicated in the write request, wherein the write request comprises respective data to be stored to the selected memory location;
determining whether the selected memory location is mapped to a respective shadow-register;
in response to determining that the selected memory location is mapped to the respective shadow-register, selecting the respective shadow-register mapped to the selected memory location, storing the data to be stored in the selected respective shadow-register and programming the data stored in the selected respective shadow-register to the selected memory location; and
in response to determining that the selected memory location is not mapped to the respective shadow-register, storing the data to be stored to the data register and programming the data stored to the data register to the selected memory location.

6. A processing system comprising:
a power supply circuit configured to receive an input voltage and provide a first supply voltage and a second supply voltage, wherein the power supply circuit is configured to selectively enable the first supply voltage when a low-power control signal is de-asserted and disable the first supply voltage when the low-power control signal is asserted;
a first sub-circuit configured to receive the first supply voltage, wherein the first sub-circuit comprises:
the OTP memory area comprising the given number N of memory slots; and
the OTP memory controller according to claim 1 , wherein the OTP memory controller is configured to manage the OTP memory area; and

a second sub-circuit configured to receive the second supply voltage.

7. The processing system according to claim 6 , further comprising a power supply monitoring circuit configured to assert the preload start signal when the first supply voltage exceeds a given threshold voltage.

8. The processing system according to claim 7 , further comprising:
a digital processing circuit;
a first resource connected to the digital processing circuit and configured to receive first configuration data; and
a reset management circuit configured to, in response to the preload end signal, start the digital processing circuit.

9. The processing system according to claim 8 , wherein the second sub-circuit comprises:
a power management circuit configured to generate the low-power control signal, and
a second resource connected to the digital processing circuit and configured to receive second configuration data.

10. The processing system according to claim 9 , wherein the power management circuit is configured to:
in response to a request received from the digital processing circuit, assert the low-power control signal, and
in response to an event signal, de-assert the low-power control signal.

11. The processing system according to claim 6 , wherein the OTP memory controller is configured to map a first memory slot of the OTP memory area storing first configuration data to a first shadow-register and a second memory slot of the OTP memory area storing second configuration data to a second shadow-register.

12. The processing system according to claim 6 , wherein the processing system is configured to:
in response to switching-on the processing system, assert the preload start signal via a power supply monitoring circuit and set the preload enable signal in order to preload first configuration data from a first memory slot to a first shadow-register and second configuration data from a second memory slot to a second shadow-register and, in response to the preload end signal, transfer the first configuration data from the first shadow-register to a first resource and the second configuration data from the second shadow-register to the second resource;
send via a digital processing circuit a request to a power management circuit in order to assert the low-power control signal thereby disabling the first supply voltage and switching off the first sub-circuit;
in response to an event signal, de-assert the low-power control signal via the power management circuit thereby enabling the first supply voltage and switching on the first sub-circuit; and
in response to switching on the first sub-circuit, assert the preload start signal via the power supply monitoring circuit and

Assignees

• St Microelectronics Srl

Inventors

• Fontana Antonino Giuseppe
• Guarnaccia Giuseppe
• Catalano Stefano

Classifications

• G06F3/0653

  Monitoring storage devices or systems · CPC title

• G06F9/30189

  according to execution mode, e.g. mode flag · CPC title

• G06F9/30116

  Shadow registers, e.g. coupled registers, not forming part of the register space · CPC title

• G06F9/3004 Primary

  to perform operations on memory · CPC title

• G06F13/1673 Primary

  using buffers · CPC title