Processing system, related integrated circuit and method

Patent metadata

Field	Value
Publication number	US-11281807-B2
Application number	US-201916403275-A
Country	US
Kind code	B2
Filing date	May 3, 2019
Priority date	May 18, 2018
Publication date	Mar 22, 2022
Grant date	Mar 22, 2022

Abstract

In one example, an integrated circuit includes a register interface that includes a plurality of registers, a bus interface configured to monitor write requests transmitted to the register interface, where the write requests include a target address and data to be written. The bus interface is configured to receive the data to be written to the plurality of registers and register selection signals for selecting a respective register in the plurality of registers. The integrated circuit includes a monitoring circuit configured to monitor the register selection signals between the bus interface and the plurality of registers in order to determine when the data to be written to the plurality of registers is valid.

First claim

What is claimed is:

1. A processing system comprising:
a non-volatile memory configured to store a firmware to be executed by a processor coupled to a bus system;
a co-processor coupled to the bus system, wherein the co-processor comprises a register interface comprising a plurality of registers and a processing circuit configured to perform a processing operation as a function of data stored in the plurality of registers, wherein the plurality of registers comprise a first set of registers configured to store a first set of configuration information and a second set of registers configured to store a second set of configuration information, wherein the register interface comprises:
a bus interface configured to monitor write requests transmitted via the bus system to the register interface, wherein the write requests comprise a target address and data to be written, wherein each register of the plurality of registers is associated with a respective address, wherein the bus interface is configured to set for each register of the plurality of registers a respective register selection signal when the target address of a write request corresponds to the address associated with the respective register, wherein each register is configured to store the data to be written when the respective register selection signal is set;

a cyclic redundancy check calculation circuit configured to compute a cyclic redundancy check value as a function of the data to be written to the first set of registers; and
a masking circuit configured to:
monitor the register selection signals associated with the registers of the first set of registers in order to determine a sequence of registers to which data has been stored;
compare the sequence of registers with a reference sequence;
when the comparison indicates that the sequence of registers corresponds to the reference sequence, providing the computed cyclic redundancy check value to the bus interface; and
when the comparison indicates that the sequence of registers does not correspond to the reference sequence, providing a value being independent from the computed cyclic redundancy check value to the bus interface.

2. The processing system according to claim 1 , wherein the cyclic redundancy check calculation circuit comprises:
a register or latch for storing the computed cyclic redundancy check value;
an XOR gate configured to generate a signal by combining the data to be written to the first set of registers and the cyclic redundancy check value stored in the register or latch; and
a combinational logic circuit configured to generate the computed cyclic redundancy check value as a function of the signal generated by the XOR gate.

3. The processing system according to claim 2 , wherein the cyclic redundancy check calculation circuit comprises a multiplexer for selecting a reference signal as a function of the register selection signals, and wherein the XOR gate is configured to generate the signal by combining the data to be written to the first set of registers, the cyclic redundancy check value stored in the register or latch and the selected reference signal.

4. The processing system according to claim 1 , wherein the processing circuit is a cryptographic processing circuit configured to perform cryptographic operations as a function of at least one cryptographic key, and wherein the first set of registers is configured to store the at least one cryptographic key.

5. The processing system according to claim 4 , wherein the non-volatile memory is arranged to store a bootloader firmware configured to store a cryptographic key to the first set of registers.

6. The processing system according to claim 4 , wherein the second set of register comprises:
a register for storing the data to be processed by the cryptographic processing circuit; and/or
a register for storing an address containing the data to be processed by the cryptographic processing circuit.

7. The processing system according to claim 6 , wherein the co-processor has associated a communication interface for interfacing a memory with the bus system, wherein the co-processor is configured to
analyze the communication exchanged between the memory and the bus system via the communication interface in order to detect a write operation to a given memory location belonging to a given memory area of the memory, and
encrypt the data received with the write operation with a cryptographic key stored in the first set of registers and store the encrypted data via the communication interface to the given memory location.

8. The processing system according to claim 6 , wherein the co-processor has associated a communication interface for interfacing a memory with the bus system, wherein the co-processor is configured to
analyze the communication exchanged between the memory and the bus system via the communication interface in order to detect a read operation to a given memory location belonging to a given memory area of the memory,
read via the communication interface the data stored at the given memory location from the memory and decrypt or encrypt the data read with a cryptographic key stored in the first set of registers.

9. The processing system according to claim 8 , wherein the memory corresponds to the non-volatile memory or a further non-volatile memory, and the memory area corresponds to a memory area for storing an application firmware to be executed by the processor.

10. The processing system according to claim 1 , wherein the register interface is configured to selectively inhibit write and/or read accesses to the first set of registers as a function of a lock signal.

11. An integrated circuit comprising:
a register interface comprising a plurality of registers,
a bus interface configured to
monitor write requests transmitted to the register interface, wherein the write requests comprise a target address and data to be written,
receive the data to be written to the plurality of registers and register selection signals for selecting a respective register in the plurality of registers; and

a monitoring circuit configured to monitor the register selection signals between the bus interface and the plurality of registers in order to determine when the data to be written to the plurality of registers is valid, wherein the monitoring circuit is configured to
compute a cyclic redundancy check value as a function of the data to be written, and
determine when the data to be written to the plurality of registers is valid by verifying the cyclic redundancy check value, and
limit access to the cyclic redundancy check value.

12. The integrated circuit according to claim 11 ,
wherein each register of the plurality of registers is associated with a respective address, wherein the bus interface is configured to set for each register of the plurality of registers a respective register selection signal when the target address of a write request corresponds to the address associated with the respective register, wherein each register is configured to store the data to be written when the respective register selection signal is set; and
wherein the monitoring circuit is configured to
monitor the register selection signals associated with the plurality of registers in order to determine a sequence of registers to which data has been stored;
compare the sequence of registers with a reference sequence;
when the comparison indicates that the sequence of registers corresponds to the reference sequence, providing the cyclic redundancy check value to the bus interface; and
when the comparison indicates that the sequence of registers does not correspond to the reference sequence, p

Assignees

• St Microelectronics Grenoble 2
• St Microelectronics Srl

Inventors

• Critelli Rosalino
• Guarnaccia Giuseppe
• Le-Goascoz Delphine
• Anquet Nicolas

Classifications

• G06F3/0659

  Command handling arrangements, e.g. command buffers, queues, command scheduling · CPC title

• G06F21/72 Primary

  in cryptographic circuits · CPC title

• G06F11/1004 Primary

  to protect a block of data words, e.g. CRC or checksum (G06F11/1076 takes precedence; security arrangements for protecting computers or computer systems against unauthorized activity G06F21/00) · CPC title

• G06F3/0623

  in relation to content · CPC title

• G06F21/85

  interconnection devices, e.g. bus-connected or in-line devices · CPC title