Method and apparatus for supporting reprogramming or reconfiguring

Patent metadata

Field	Value
Publication number	US-9660936-B2
Application number	US-201414516300-A
Country	US
Kind code	B2
Filing date	Oct 16, 2014
Priority date	Oct 18, 2013
Publication date	May 23, 2017
Grant date	May 23, 2017

Abstract

A method includes setting a first indicator to a first value, which causes an apparatus to stop receiving traffic from a traffic source. At least one register is accessed to read or write at least one new value, and a second indicator is set indicating that accessing of the at least one register has completed. The first indicator is set to a second value. When the first indicator has the second value and the second indicator is set, the apparatus is again allowed to receive traffic from the traffic source.

First claim

The invention claimed is:

1. A method, comprising:
setting a first indicator to a first value, the first indicator including at least one of a transmitted request to stop traffic, a transmitted denial to start traffic, an ignored transmitted request to start traffic, and a first memory storage location;
causing an apparatus to stop receiving traffic from a traffic source based on said setting the first indicator to the first value;
accessing at least one register to read or write at least one new value;
setting a second indicator to a second value to indicate that said act of accessing the at least one register has completed;
setting said first indicator to a third value; and
allowing said apparatus to receive traffic from said traffic source based on said first indicator having the third value and said second indicator having the second value.

2. A method as claimed in claim 1 , wherein at least one of said first and second indicators includes a flag.

3. A method as claimed in claim 1 , wherein said at least one register includes a control register.

4. A method as claimed in claim 1 , comprising:
providing a plurality of sets of registers, each set of registers associated with a service, said act of accessing the at least one register including the act of accessing at least one register of at least one set.

5. A method as claimed in claim 1 , comprising:
polling said second indicator to determine if said act of accessing the at least one register has completed.

6. A method as claimed in claim 1 , wherein said act of setting the first indicator to the third value is dependent on a value of one or more further second indicators.

7. A method as claimed in claim 1 , wherein said act of setting the first indicator to at least one value is by a controller.

8. A method as claimed in claim 1 , wherein said act of setting the first indicator to at least one value is by a CPU.

9. A method as claimed in claim 1 , comprising:
providing a plurality of first indicators wherein said first indicator is one of the plurality of first indicators.

10. A method as claimed in claim 1 , comprising:
completing or flushing from a buffer each transaction associated with traffic received from the traffic source before said traffic was stopped, said completing or flushing being performed prior to the act of setting said first indicator to the third value.

11. An apparatus, comprising:
an input configured to receive traffic from a traffic source;
a first indicator, the first indicator including at least one of a transmitted request to stop traffic, a transmitted denial to start traffic, an ignored transmitted request to start traffic, and a first memory storage location;
a second indicator;
at least one register; and
a controller configured to control said apparatus, said control including:
setting said first indicator to a first value to cause said apparatus to stop receiving traffic from said traffic source;
setting said second indicator to a second value to indicate that an access to read or write at least one new value of at least one of said at least one register has completed; and
setting said first indicator to a third value;

wherein when said second indicator has the second value and said first indicator has the third value, said controller is configured to allow said apparatus to receive traffic from said traffic source.

12. An apparatus as claimed in claim 11 , wherein at least one of said first and second indicators includes a flag.

13. An apparatus as claimed in claim 11 , wherein said at least one register includes a control register.

14. An apparatus as claimed in claim 11 , comprising:
a plurality of sets of registers, each set of registers associated with a service, said at least one register being a member of at least one set of registers of the plurality of sets of registers.

15. An apparatus as claimed in claim 11 , comprising:
an interface configured to receive a polling request for said second indicator to determine if said access of said at least one of said at least one register has completed, said interface further configured to provide a response to said polling request.

16. An apparatus as claimed in claim 15 , wherein said interface is configured to receive said polling request from a second controller.

17. An apparatus as claimed in claim 11 , comprising:
an interface configured to receive information dependent on a value of one or more further second indicators, wherein setting said first indicator to the third value is dependent on said information.

18. An apparatus as claimed in claim 17 , wherein said interface is configured to receive said information dependent on the value of one or more further second indicators from a second controller.

19. An apparatus as claimed in claim 16 , wherein said second controller comprises a CPU.

20. An apparatus as claimed in claim 11 , wherein said first indicator is one of a plurality of first indicators available to be set.

21. An apparatus as claimed in claim 11 , comprising:
a buffer, wherein control of said apparatus by said controller includes:
completing or flushing from said buffer each transaction associated with traffic received from the traffic source before said traffic was stopped prior to setting said first indicator to the third value.

22. An integrated circuit, comprising:
a traffic source;
an interconnect; and
a network interface, said network interface configured to receive traffic from said traffic source and output said traffic from said network interface onto said interconnect, said network interface including:
a first indicator, the first indicator including at least one of a transmitted request to stop traffic, a transmitted denial to start traffic, an ignored transmitted request to start traffic, and a first memory storage location;
at least one register; and
a controller configured to control said integrated circuit, said control including:
setting said first indicator to a first value to cause said network interface to stop receiving traffic from said traffic source;
determining that an access to said at least one register has completed; and
allowing said network interface to receive traffic from said traffic source based on said determining that the access to said at least one register is completed.

23. An integrated circuit as claimed in claim 22 , comprising:
a programming interface;
a plurality of shadow registers coupled to the programming interface and configured to store reprogramming data to be written to the at least one register after said network interface stops receiving traffic from said traffic source.

24. An integrated circuit as claimed in claim 23 , wherein said programming interface is arranged to pass reconfiguration data into the network interface, said reconfiguration data arranged to reprogram at least one feature of the network interface, said at least one feature drawn from a set of features including a quality of service feature, an address interleaving feature, a routing feature, a security address feature, an interleaving on/off feature, an address interleaving start/end feature, an address interleaving step feature, a bandwidth feature, and a destination feature.

25. An integrated circuit as claimed in claim 23 , wherein said programming interface is arranged to pass reconfiguration data into the network interface, said reconfiguration data arranged to maintain coher

Assignees

• Stmicroelectronics (Grenoble 2) Sas
• St Microelectronics Srl

Inventors

• Locatelli Riccardo
• Soulie Michael
• Giotta Francesco
• Guarrasi Raffaele
• Guarnaccia Giuseppe

Classifications

• G06F15/17312 Primary

  Routing techniques specific to parallel machines, e.g. wormhole, store and forward, shortest path problem congestion (routing on a LAN H04L45/00) · CPC title

• H04L47/24

  Traffic characterised by specific attributes, e.g. priority or QoS · CPC title

• H04L49/109 Primary

  Integrated on microchip, e.g. switch-on-chip · CPC title

• G06F13/128 Primary

  for dedicated transfers to a network (for protocol converters G06F13/387) · CPC title

• G06F13/42

  Bus transfer protocol, e.g. handshake; Synchronisation · CPC title