Method and apparatus for use with different memory maps

Patent metadata

Field	Value
Publication number	US-10419432-B2
Application number	US-201415026588-A
Country	US
Kind code	B2
Filing date	Oct 17, 2014
Priority date	Oct 18, 2013
Publication date	Sep 17, 2019
Grant date	Sep 17, 2019

Abstract

An apparatus has a data store configured to store access activity information. The access activity information indicates which one or more of a plurality of different access parameter sets is active. The data store is also configured to store access defining information, which defines, at least for each active access parameter set, a number of channels, location information of said channels, and interleaving information associated with said channels.

First claim

The invention claimed is:

1. An integrated circuit apparatus, comprising:
at least two network interfaces;
at least two routers;
at least two links configured to pass packet-based communications, the at least two links coupling the at least two network interfaces through the at least two routers; and
a processor to control programming of the at least two network interfaces based on a data store, the data store configured to store electronic device access activity information and electronic device access defining information, the electronic device access activity information indicating which one or more of a plurality of different electronic device access parameter sets is active and said electronic device access defining information defining at least for each active electronic device access parameter set:
a number of channels formed in one or more sequences of adjacent contiguous memory ranges, wherein each channel is arranged to pass packet-based data via one or more of the at least two links, one or more of the at least two routers, and one or more of the at least two network interfaces,
location information of said channels, and
interleaving information associated with said channels.

2. The integrated circuit apparatus as claimed in claim 1 , wherein interleaving information comprises at least one of interleaving step size and location of an interleaved region in a channel.

3. The integrated circuit apparatus as claimed in claim 2 , wherein said location of an interleaved region is defined by at least one of a start location and an end location.

4. The integrated circuit apparatus as claimed in claim 1 , wherein said electronic device access defining information comprises quality of service information.

5. The integrated circuit apparatus as claimed in claim 1 , comprising a determination block configured to receive an input address, said determination block configured to determine which electronic device access parameter set said input address is associated and to provide channel information associated with said input address.

6. The integrated circuit apparatus as claimed in claim 5 , wherein said determination block has an electronic device access parameter set determiner configured to receive said input address and location information from said data store, said electronic device access parameter set determiner configured, based on said input address and said location information, to provide an output to a channel information provider.

7. The integrated circuit apparatus as claimed in claim 6 , wherein said electronic device access parameter set determiner comprises an address comparator configured to receive said input address and address range information and to provide an output to said channel information provider.

8. The integrated circuit apparatus as claimed in claim 6 , wherein said electronic device access parameter set determiner is configured to receive said electronic device access activity information.

9. The integrated circuit apparatus as claimed in claim 6 , wherein said channel information provider comprises at least one table configured to provide said channel information.

10. The integrated circuit apparatus as claimed in claim 9 , wherein said at least one table comprises channel number information.

11. The integrated circuit apparatus as claimed in claim 9 , wherein said at least one table comprises channel position information.

12. The integrated circuit apparatus as claimed in claim 6 , wherein said electronic device access parameter set determiner is configured to provide a control signal, said channel information provider configured to use said control signal to cause channel information for said determined electronic device access parameter set to be output.

13. The integrated circuit apparatus as claimed in claim 6 , wherein said channel information comprises at least one of channel position, channel number, interleaving step size, and quality of service.

14. The integrated circuit apparatus as claimed in claim 6 , comprising a destination arrangement, said destination arrangement configured to determine a destination in dependence on said input address and channel information.

15. A method of configuring, by an integrated circuit of an apparatus, said method comprising:
providing at least two network interfaces;
providing at least two routers;
providing at least two links configured to pass packet-based communications, the at least two links coupling the at least two network interfaces through the at least two routers; and
providing a processor to control programming of the at least two network interfaces based on activity information provided for said apparatus indicating which one or more of a plurality of different electronic device access parameter sets is active, wherein electronic device access defining information for each active electronic device access parameter set, comprises:
a number of channels formed in one or more sequences of adjacent contiguous memory ranges, wherein each channel is arranged to pass packet-based data via one or more of the at least two links, one or more of the at least two routers, and one or more of the at least two network interfaces,
location information of said channels, and
interleaving information associated with said channels.

16. The method as claimed in claim 15 , wherein interleaving information comprises at least one of interleaving step size and location of an interleaved region in a channel.

17. The method as claimed in claim 16 , wherein said location of an interleaved region is defined by at least one of a start location and an end location.

18. The method as claimed in claim 15 , wherein said electronic device access defining information comprises quality of service information.

19. The method as claimed in claim 15 , comprising:
receiving an input address;
determining with which electronic device access parameter set said input address is associated; and
providing channel information associated with said input address.

20. The method as claimed in claim 19 , comprising:
using said input address and location information to provide a channel information output.

21. The method as claimed in claim 20 , comprising:
comparing said input address and address range information to provide said channel information output.

22. The method as claimed in claim 19 , comprising:
providing a control signal to a channel information provider to cause channel information for said determined electronic device access parameter set to be output.

23. The method as claimed in claim 19 , wherein said channel information comprises at least one of channel position, channel number, interleaving step size, and quality of service.

24. The method as claimed in claim 19 , comprising:
determining a destination in dependence on said input address and channel information.

25. A non-transitory computer readable medium arranged to store instructions that administer a computer aided design tool, the instructions configured to perform a method to configure a device, the method comprising:
generating computer code to represent a default version of the device, wherein the default version of the device includes a plurality of different networks formed via at least two network interfaces, at least two routers, at least two links coupling the at least two network interfaces through the at least two routers, and a processor to control programming of the

Assignees

• St Microelectronics Sa
• St Microelectronics Grenoble 2
• St Microelectronics Srl
• Stmicroelectronics Grenoble2 Sas

Inventors

• Soulie Michael
• Locatelli Riccardo
• Catalano Valerio
• Ferjani Hajer
• Maruccia Giuseppe
• Guarrasi Raffaele
• Guarnaccia Giuseppe

Classifications

• G06F12/0646 Primary

  Configuration or reconfiguration · CPC title

• G06F2213/0038

  System on Chip · CPC title

• G06F12/0607 Primary

  Interleaved addressing · CPC title

• H04L63/10 Primary

  for controlling access to devices or network resources · CPC title

• G06F15/7857

  using interleaved memory (addressing G06F12/0607) · CPC title