Register shielding in semiconductor devices

Patent metadata

Field	Value
Publication number	US-12307002-B2
Application number	US-202217882400-A
Country	US
Kind code	B2
Filing date	Aug 5, 2022
Priority date	Aug 17, 2021
Publication date	May 20, 2025
Grant date	May 20, 2025

Abstract

A semiconductor device comprises one or more registers having digital signals stored therein. The semiconductor device is configured for communication with one or more external devices and such communication may involve requests for access to portions of these register or registers. Register shield circuitry is provided comprising access detection circuitry configured to detect requests for access to these register portions in communication with the external device or devices. The register shield circuitry is configured to be selectively activated in a register shield mode to shield these register portions from undesired requests for access. When activated in the register shield mode, the register shield circuitry prevents access to these register portions in response to requests for access detected by the access detection circuitry.

First claim

The invention claimed is:

1. A semiconductor device, comprising:
a set of registers, which, in operation, store digital data;
an interface coupled to the set of registers, wherein the interface, in operation, receives external requests to access registers of the set of registers; and
selectively-activateable register shield circuitry, coupled between the interface and the set of registers, wherein the register shield circuitry, in response to activation, in operation:
intercepts requests received by the interface and directed to a register of the set of registers;
determines whether an intercepted request is directed to a portion of a register of the set of registers to which access is prohibited; and
responds to a determination that the intercepted request is directed to a portion of a register of the set of registers to which access is prohibited by preventing access to data stored in the portion of the register of the set of registers, wherein the preventing access to data stored in the portion of the register of the set of registers comprises applying a bit masking pattern to data returned in response to the request for access.

2. The semiconductor device of claim 1 , comprising one-time-programmable, OTP cells configured to control activation of the register shield circuitry.

3. The semiconductor device of claim 2 , wherein the one-time-programmable, OTP cells comprise electronic fuses.

4. The semiconductor device of claim 1 , comprising interconnect circuitry including the interface and the register shield circuitry.

5. The semiconductor device of claim 4 , wherein the interconnect circuitry has a protocol bridge and the register shield circuitry is included in said protocol bridge.

6. The semiconductor device of claim 4 , wherein the register shield circuitry is included in an interconnect bridge or decoder in said interconnect circuitry.

7. The semiconductor device of claim 1 , wherein the register shield circuitry has a register mask mode, and the register shield circuitry, in response to activation in the register mask mode indicating a portion of a register of the set of registers is to be masked, in operation:
in response to a request for access to the indicated portion of the register, applies the bit masking pattern to data returned in response to the request for access.

8. The semiconductor device of claim 1 , wherein said bit masking pattern comprises logic inversion of selected ones of the bits in the data returned in response to the request.

9. The semiconductor device of claim 1 , wherein the register stores a plurality of bits of data, and the portion of the register is a subset of bits of the plurality of bits.

10. The semiconductor device of claim 1 , wherein the preventing access to data stored in the portion of the register of the set of registers comprising responding to the received request with dummy data.

11. A method, comprising:
determining whether registry shield circuitry coupled between an interface of an integrated circuit and a set of registers of the integrated circuit has been activated;
in response to a determination that the registry shield circuitry has been activated:
intercepting requests received by the interface and directed to a register of the set of registers;
determining whether an intercepted request is directed to a portion of a register of the set of registers to which access is prohibited; and
responding to a determination that the intercepted request is directed to a portion of a register of the set of registers to which access is prohibited by preventing access to data stored in the portion of the register of the set of registers; and

in response to a determination that the registry shield circuitry has not been activated, responding to requests received by the interface and directed to a register of the set of registers by accessing the register of the set of registers, wherein,
the register shield circuitry has a register mask mode indicating a portion of a register of the set of registers is to be masked; and
in the register mask mode, the preventing access comprises applying a bit masking pattern to data returned in response to a request for access to the indicated portion of the register of the set of registers.

12. The method of claim 11 , comprising activating the registry shield circuitry.

13. The method of claim 12 , wherein activating the registry shield circuitry comprising programming one-time-programmable, OTP cells.

14. The method of claim 13 , wherein the one-time-programmable, OTP cells comprise electronic fuses.

15. The method of claim 11 , wherein the register stores a plurality of bits of data, and the portion of the register is a subset of bits of the plurality of bits.

16. The method of claim 11 , wherein the preventing access to data stored in the portion of the register of the set of registers comprises responding to the received request with dummy data.

17. The method of claim 11 , wherein the bit masking pattern comprises logic inversion of selected ones of the bits in the data returned in response to the request.

18. A system, comprising:
a plurality of processing circuits, each including a set of registers, wherein the registers, in operation, store data;
one or more interfaces, which, in operation, receive requests to access registers of the plurality of processing circuits; and
a plurality of registry shield circuits coupled between processing circuits of the plurality of processing circuits and interfaces of the one or more interfaces, the plurality of registry shield circuits including a set of activated registry shield circuits and a set of unactivated registry shield circuits, wherein:
an activated registry shield circuit of the set of activated registry shield circuits, in operation:
intercepts received requests directed to registers of processing circuits coupled to the activated registry shield circuit;
determines whether an intercepted request is directed to a portion of a register to which access is prohibited; and
responds to a determination that the intercepted request is directed to a portion of a register to which access is prohibited by preventing access to data stored in the portion of the register; and

an unactivated registry shield circuit of the set of unactivated registry shield circuits, in operation, forwards received requests directed to registers of processing circuits coupled to the unactivated registry shield circuit to the respective processing circuits, wherein,
the activated register shield circuit has a register mask mode indicating a portion of a register of the set of registers is to be masked; and
in the register mask mode, the preventing access comprises applying a bit masking pattern to data returned in response to a request for access to the indicated portion of the register of the set of registers.

19. The system of claim 18 , comprising an integrated circuit including the plurality of processing circuits, the one or more interfaces, and the plurality of registry shield circuits.

20. The system of claim 18 , wherein each registry shield circuit of the plurality of registry shield circuits comprises a plurality of one-time-programmable, OTP cells, which, in operation, store activation information associated with the register shield circuit.

21. The system of claim 18 , wherein the bit masking pattern comprises logic inversion of selected ones of the bits in the data returned in response to the request.

22. A non-transitory computer-r

Assignees

• St Microelectronics Srl

Inventors

• Rosselli Salvatore Marco
• Guarnaccia Giuseppe

Classifications

• G06F21/74 Primary

  operating in dual or compartmented mode, i.e. at least one secure mode · CPC title

• G06F21/79

  in semiconductor storage media, e.g. directly-addressable memories · CPC title

• G06F21/604

  Tools and structures for managing or administering access control systems · CPC title

• G06F2221/2141

  Access rights, e.g. capability lists, access control lists, access tables, access matrices · CPC title

• G06F21/76 Primary

  in application-specific integrated circuits [ASIC] or field-programmable devices, e.g. field-programmable gate arrays [FPGA] or programmable logic devices [PLD] · CPC title