Binary-to-gray conversion circuit, related FIFO memory, integrated circuit and method

Patent metadata

Field	Value
Publication number	US-10635394-B2
Application number	US-201916256449-A
Country	US
Kind code	B2
Filing date	Jan 24, 2019
Priority date	Feb 23, 2018
Publication date	Apr 28, 2020
Grant date	Apr 28, 2020

Abstract

A circuit and method for performing a Binary-to-Gray conversion are disclosed. A first binary signal represents a target value and a second binary signal is stored in a register. A set of binary candidate values are determined where the respective Gray equivalent of each binary candidate value has a Hamming distance of one from the Gray equivalent of the second binary value. One of the binary candidate values is selected as a function of the first binary signal and the second binary signal. The selected binary candidate value is provided at input to the register. An encoded signal is generated by determining the Gray encoded equivalent of the selected binary candidate value.

First claim

What is claimed is:

1. A binary-to-gray conversion circuit, comprising:
an input configured to receive a first binary signal;
a register configured to store a second binary signal;
a prediction circuit configured to receive the second binary signal and to provide a set of binary candidate values, wherein a respective Gray equivalent of each binary candidate value has a Hamming distance of one from a Gray equivalent of the second binary signal;
an arbiter configured to select one of the binary candidate values as a function of the first binary signal and the second binary signal, wherein the selected binary candidate value is provided to the register; and
an encoder block configured to receive the selected binary candidate value and output a Gray encoded equivalent of the selected binary candidate value.

2. The circuit according to claim 1 , wherein the first binary signal, the second binary signal and the Gray encoded equivalent of the selected binary candidate value each have a given number k of bits, and the prediction circuit is configured to provide k binary candidate values.

3. The circuit according to claim 2 , wherein the prediction circuit comprises k sub-circuits, each configured to provide at output an i-th binary candidate value, with i=1 . . . k.

4. The circuit according to claim 3 , wherein the prediction circuit comprises a first circuit configured to receive the second binary signal and to provide a first signal by computing the difference between (2 k −1) and the value of the second binary signal.

5. The circuit according to claim 4 , wherein each the sub-circuit comprises:
an input configured to receive the second binary signal;
a second circuit configured to generate a second signal by selecting the (k−i) most significant bits of the second binary signal;
a third circuit configured generate a third signal by selecting the i least significant bits of the first signal; and
a fourth circuit configured to generate the respective binary candidate value by combining the second signal and the third signal.

6. The circuit according to claim 3 , wherein the prediction circuit comprises a first circuit configured to receive the second binary signal and to provide a first signal by inverting the bits of the second binary signal.

7. The circuit according to claim 6 , wherein each the sub-circuit comprises:
an input configured to receive the second binary signal;
a second circuit configured to generate a second signal by selecting the (k−i) most significant bits of the second binary signal;
a third circuit configured generate a third signal by selecting the i least significant bits of the first signal; and
a fourth circuit configured to generate the respective binary candidate value by combining the second signal and the third signal.

8. The circuit according to claim 1 , wherein the arbiter is associated with a preprocessing circuit configured to select the binary candidate values of the set of binary candidate values that are between the value of the second binary signal and the value of the first binary signal, the value of the second binary signal representing a lower limit and the value of the first binary signal representing an upper limit or target value.

9. The circuit according to claim 8 , wherein the preprocessing circuit comprises, for each binary candidate value, a respective out-of-range circuit, each configured to generate a respective mask signal indicating whether the respective binary candidate value is between the lower and the upper limit.

10. The circuit according to claim 9 , wherein the arbiter is configured to disregard binary candidate values having a respective mask signal indicating that the respective binary candidate value is not between the lower and the upper limit.

11. The circuit according to claim 9 , wherein the arbiter is configured to disregard the binary candidate values having a distance from the second binary signal that is greater than a given maximum distance.

12. The circuit according to claim 1 , wherein the arbiter is configured to select the binary candidate value having the greatest value.

13. The circuit according to claim 1 , wherein the arbiter is implemented with a combinational logic circuit.

14. A FIFO memory comprising:
a memory area comprising a plurality of memory locations;
a write interface configured to generate a binary write pointer indicating a memory location for writing data to the memory area;
a read interface configured to generate a binary read pointer indicating a memory location for reading data from the memory area;
a synchronization circuit configured to exchange the binary write pointer or the binary read pointer between the write interface and the read interface, wherein the synchronization circuit is configured to exchange Gray coded signals; and
a binary-to-gray conversion circuit configured to receive the binary write pointer or the binary read pointer, wherein a Gray encoded equivalent of a binary candidate value determined by the Binary-to-Gray conversion circuit is provided to the synchronization circuit.

15. The FIFO memory according to claim 14 , wherein the binary-to-gray conversion circuit comprises:
a register configured to store a second binary signal;
a prediction circuit configured to receive the second binary signal and to provide a set of binary candidate values, wherein a respective Gray equivalent of each binary candidate value has a Hamming distance of one from a Gray equivalent of the second binary signal;
an arbiter configured to select one of the binary candidate values as a function of a first binary signal and the second binary signal, wherein the first binary signal is the binary write pointer or the binary read pointer and wherein the selected binary candidate value is provided to the register; and
an encoder block configured to receive the selected binary candidate value and output a Gray encoded equivalent of the selected binary candidate value.

16. A method of performing a Binary-to-Gray conversion, the method comprising:
receiving a first binary signal representing a target value;
storing a second binary signal in a register;
determining a set of binary candidate values, wherein the Gray equivalent of each respective binary candidate value has a Hamming distance of one from the Gray equivalent of the second binary value;
selecting one of the binary candidate values as a function of the first binary signal and the second binary signal, wherein the selected binary candidate value is provided at input to the register; and
generating an encoded signal by determining the Gray encoded equivalent of the selected binary candidate value.

17. The method according to claim 16 , wherein the first binary signal, the second binary signal and the Gray encoded equivalent of the selected binary candidate value each have a given number k of bits, and the set of binary candidate values has the k binary candidate values.

18. The method according to claim 16 , wherein selecting one of the binary candidate values comprises selecting the binary candidate values of the set of binary candidate values that are between the value of the second binary signal and the value of the first binary signal, the value of the second binary signal representing a lower limit and the value of the first binary signal representing an upper limit or target value.

19. The method according to claim 18 , further comprising, for each binary candidate value generating a respective mask signal indicating whether the respective binary candidate value i

Assignees

• St Microelectronics Srl

Inventors

• Rosselli Salvatore Marco
• Guarnaccia Giuseppe

Classifications

• G11C7/1018

  Serial bit line access mode, e.g. using bit line address shift registers, bit line address counters, bit line burst counters · CPC title

• G06F5/06

  for changing the speed of data flow, i.e. speed regularising {or timing, e.g. delay lines, FIFO buffers; over- or underrun control therefor (G06F7/78 takes precedence)} · CPC title

• H03M7/16 Primary

  Conversion to or from unit-distance codes, e.g. Gray code, reflected binary code · CPC title

• G11C7/222

  Clock generating, synchronizing or distributing circuits within memory device · CPC title

• G06F5/14 Primary

  for overflow or underflow handling, e.g. full or empty flags · CPC title