Bi-synchronous electronic device and FIFO memory circuit with jump candidates and related methods

Patent metadata

Field	Value
Publication number	US-9311975-B1
Application number	US-201414508321-A
Country	US
Kind code	B1
Filing date	Oct 7, 2014
Priority date	Oct 7, 2014
Publication date	Apr 12, 2016
Grant date	Apr 12, 2016

Abstract

A bi-synchronous electronic device may include a FIFO memory circuit, and a first digital circuit coupled to the FIFO memory circuit and configured to operate based upon a first clock signal, and write to the FIFO memory circuit based upon a write pointer. The bi-synchronous electronic device may include second digital circuit coupled to the FIFO memory circuit and configured to operate based upon a second clock signal different from the first clock signal, and read from the FIFO memory circuit based upon a read pointer. The FIFO memory circuit may be configured to detect a jump in the write pointer to a new position, determine jump candidates for the read pointer from a current position, select a jump candidate, and synchronize the read pointer based upon the selected jump candidate.

First claim

That which is claimed is:

1. A bi-synchronous electronic device comprising:
a first-in-first-out (FIFO) memory circuit;
a first digital circuit coupled to said FIFO memory circuit and configured to
operate based upon a first clock signal, and
write to said FIFO memory circuit based upon a write pointer; and

a second digital circuit coupled to said FIFO memory circuit and configured to
operate based upon a second clock signal different from the first clock signal, and
read from said FIFO memory circuit based upon a read pointer;

said FIFO memory circuit configured to
detect a jump in the write pointer to a new position,
determine a plurality of jump candidates for the read pointer from a current position,
select a jump candidate from the plurality thereof, and
synchronize the read pointer based upon the selected jump candidate.

2. The bi-synchronous electronic device of claim 1 wherein each jump candidate comprises a Gray encoding jump candidate for the read pointer from the current position.

3. The bi-synchronous electronic device of claim 1 wherein said FIFO memory circuit is configured to select the jump candidate based upon a distance between the new position and respective positions of the plurality of jump candidates.

4. The bi-synchronous electronic device of claim 1 wherein said FIFO memory circuit is configured to discard jump candidates with respective positions less than the current position and greater than the new position.

5. The bi-synchronous electronic device of claim 1 wherein said FIFO memory circuit is configured to synchronize the read pointer by Gray encoded incrementing the read pointer from a respective position of the selected jump candidate to the new position.

6. The bi-synchronous electronic device of claim 1 wherein said FIFO memory circuit is configured to, when an additional jump in the write pointer is detected, determine a second plurality of jump candidates for the read pointer from a respective position of the selected jump candidate.

7. The bi-synchronous electronic device of claim 1 wherein said FIFO memory circuit comprises processing circuitry, and a memory core coupled to said processing circuitry and configured to store data for transfer from said first digital circuit to said second digital circuit.

8. The bi-synchronous electronic device of claim 1 wherein the jump in the write pointer to the new position comprises a non-consecutive jump from the current position.

9. The bi-synchronous electronic device of claim 1 wherein said FIFO memory circuit comprises a 16-128 bit bi-synchronous FIFO memory.

10. A first-in-first-out (FIFO) memory circuit to be coupled in a bi-synchronous electronic device comprising a first digital circuit operating based upon a first clock signal, and writing to the FIFO memory circuit based upon a write pointer, and a second digital circuit operating based upon a second clock signal different from the first clock signal, and reading from the FIFO memory circuit based upon a read pointer, the FIFO memory circuit comprising:
processing circuitry, and a memory core coupled to said processing circuitry and configured to
store data for transfer from the first digital circuit to the second digital circuit,
detect a jump in the write pointer to a new position,
determine a plurality of jump candidates for the read pointer from a current position,
select a jump candidate from the plurality thereof, and
synchronize the read pointer based upon the selected jump candidate.

11. The FIFO memory circuit of claim 10 wherein each jump candidate comprises a Gray encoding jump candidate for the read pointer from the current position.

12. The FIFO memory circuit of claim 10 wherein said processing circuitry is configured to select the jump candidate based upon a distance between the new position and respective positions of the plurality of jump candidates.

13. The FIFO memory circuit of claim 10 wherein said processing circuitry is configured to discard jump candidates with respective positions less than the current position and greater than the new position.

14. The FIFO memory circuit of claim 10 wherein said processing circuitry is configured to synchronize the read pointer by Gray encoded incrementing the read pointer from a respective position of the selected jump candidate to the new position.

15. The FIFO memory circuit of claim 10 wherein said FIFO memory circuit is configured to, when an additional jump in the write pointer is detected, determine a second plurality of jump candidates for the read pointer from a respective position of the selected jump candidate.

16. The FIFO memory circuit of claim 10 wherein the jump in the write pointer to the new position comprises a non-consecutive jump from the current position.

17. A method of operating a bi-synchronous electronic device comprising a first-in-first-out (FIFO) memory circuit, the method comprising:
using a first digital circuit coupled to the FIFO memory circuit to
operate based upon a first clock signal, and
write to the FIFO memory circuit based upon a write pointer;

using a second digital circuit coupled to the FIFO memory circuit to
operate based upon a second clock signal different from the first clock signal, and
read from the FIFO memory circuit based upon a read pointer; and

using the FIFO memory circuit to
detect a jump in the write pointer to a new position,
determine a plurality of jump candidates for the read pointer from a current position,
select a jump candidate from the plurality thereof, and
synchronize the read pointer based upon the selected jump candidate.

18. The method of claim 17 wherein each jump candidate comprises a Gray encoding jump candidate for the read pointer from the current position.

19. The method of claim 17 further comprising using the FIFO memory circuit to select the jump candidate based upon a distance between the new position and respective positions of the plurality of jump candidates.

20. The method of claim 17 further comprising using the FIFO memory circuit to discard jump candidates with respective positions less than the current position and greater than the new position.

21. The method of claim 17 further comprising using the FIFO memory circuit to synchronize the read pointer by Gray encoded incrementing the read pointer from a respective position of the selected jump candidate to the new position.

22. The method of claim 17 further comprising using the FIFO memory circuit to, when an additional jump in the write pointer is detected, determine a second plurality of jump candidates for the read pointer from a respective position of the selected jump candidate.

Assignees

• St Microelectronics Srl

Inventors

• Rosselli Salvatore Marco
• Guarnaccia Giuseppe
• Mari Ugo

Classifications

• G06F5/06

  for changing the speed of data flow, i.e. speed regularising {or timing, e.g. delay lines, FIFO buffers; over- or underrun control therefor (G06F7/78 takes precedence)} · CPC title

• G06F2205/102

  Avoiding metastability, i.e. preventing hazards, e.g. by using Gray code counters · CPC title

• G11C7/222 Primary

  Clock generating, synchronizing or distributing circuits within memory device · CPC title

• G06F5/10 Primary

  having a sequence of storage locations each being individually accessible for both enqueue and dequeue operations, e.g. using random access memory {(G06F5/065 takes precedence)} · CPC title