Embedded Package with Shielding Pad
US-2026018427-A1 · Jan 15, 2026 · US
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Fehler Robert patents
Fehler Robert is listed as an inventor on 29 patents in our database. Major assignees and classification codes are summarized below.
| Metric | Value |
|---|---|
| Inventor | Fehler Robert |
| Total patents | 29 |
| First publication | Dec 27, 2018 |
| Latest publication | Jan 15, 2026 |
Notable patents
Publications ranked by popularity score, then publication date.
Embedded package with shielding pad
US-12431367-B2 · Sep 30, 2025 · US
Power stage package with half bridge-connected transistor chips and driver chip having through connection
US-2025183232-A1 · Jun 5, 2025 · US
Method for fabricating a semiconductor package
US-2025087581-A1 · Mar 13, 2025 · US
Semiconductor devices including parallel electrically conductive layers
US-12237246-B2 · Feb 25, 2025 · US
Semiconductor package with non-uniformly distributed vias
US-12159829-B2 · Dec 3, 2024 · US
Semiconductor package and passive element with interposer
US-12131988-B2 · Oct 29, 2024 · US
Embedded Package with Shielding Pad
US-2024312799-A1 · Sep 19, 2024 · US
Semiconductor module having a multi-branch switch node connector
US-12009290-B2 · Jun 11, 2024 · US
Circuitry and method of forming a circuitry
US-11935874-B2 · Mar 19, 2024 · US
Recent patents
Latest publications not already listed above.
Semiconductor Package and Passive Element with Interposer
US-2024079310-A1 · Mar 7, 2024 · US
Semiconductor package and passive element with interposer
US-11848262-B2 · Dec 19, 2023 · US
Semiconductor module having a multi-branch switch node connector
US-2023253304-A1 · Aug 10, 2023 · US
Semiconductor module
US-11664304-B2 · May 30, 2023 · US
Semiconductor package with non-uniformly distributed vias
US-2022367350-A1 · Nov 17, 2022 · US
Space efficient and low parasitic half bridge
US-11469164-B2 · Oct 11, 2022 · US
Semiconductor package and method of manufacturing a semiconductor package
US-11444017-B2 · Sep 13, 2022 · US
Semiconductor Package and Passive Element with Interposer
US-2022262716-A1 · Aug 18, 2022 · US
Semiconductor package and method of manufacturing a semiconductor package
US-11348861-B2 · May 31, 2022 · US
Semiconductor module
US-2022108945-A1 · Apr 7, 2022 · US
Circuitry and Method of Forming a Circuitry
US-2022028840-A1 · Jan 27, 2022 · US
Semiconductor devices including parallel electrically conductive layers
US-2021287964-A1 · Sep 16, 2021 · US
Space Efficient and Low Parasitic Half Bridge
US-2021225745-A1 · Jul 22, 2021 · US
Electronic device including redistribution layer pad having a void
US-10916484-B2 · Feb 9, 2021 · US
Semiconductor Package and Method of Manufacturing a Semiconductor Package
US-2021005536-A1 · Jan 7, 2021 · US
Semiconductor package and method of manufacturing a semiconductor package
US-10811342-B2 · Oct 20, 2020 · US
Semiconductor Package and Method of Manufacturing a Semiconductor Package
US-2020075484-A1 · Mar 5, 2020 · US
Semiconductor Package and Method of Manufacturing a Semiconductor Package
US-2019267309-A1 · Aug 29, 2019 · US
Electronic device including redistribution layer pad having a void
US-2018374769-A1 · Dec 27, 2018 · US
Major assignees
Companies most often associated with this inventor's publications.
| Assignee | Patents |
|---|---|
| Infineon Technologies Ag | 16 |
| Infineon Technologies Austria Ag | 13 |
Top CPC classifications
Most common classification codes across this inventor's patents.
| CPC | Patents |
|---|---|
| H10W70/60 | 21 |
| H10W90/00 | 16 |
| H10W72/944 | 15 |
| H10W72/9413 | 15 |
| H10W70/611 | 14 |