Semiconductor package and method of manufacturing a semiconductor package

Patent metadata

Field	Value
Publication number	US-10811342-B2
Application number	US-201916287318-A
Country	US
Kind code	B2
Filing date	Feb 27, 2019
Priority date	Feb 28, 2018
Publication date	Oct 20, 2020
Grant date	Oct 20, 2020

Abstract

A semiconductor package includes a semiconductor die having a semiconductor device, and first and second contact pads arranged on opposite surfaces of the die. The semiconductor die is embedded in a dielectric layer. The semiconductor package also includes one or more first package contact pads and one or more second package contact pads arranged on a first major surface of the semiconductor package. The first contact pad of the die is coupled to the one or more first package contact pads, and the second contact pad of the die is coupled to the one or more second package contact pads. In operation, the semiconductor device causes a current path between the first contact pad and the second contact pad. The package contact pads are arranged on the first major surface of the semiconductor package to provide multiple non-parallel current paths.

First claim

What is claimed is:

1. A semiconductor package, comprising:
a semiconductor die comprising a semiconductor device, a first contact pad arranged on a first surface of the semiconductor die and a second contact pad arranged on a second surface of the semiconductor die that opposes the first surface, the semiconductor die being embedded in a dielectric layer; and
one or more first package contact pads and one or more second package contact pads arranged on a first major surface of the semiconductor package, the first contact pad of the semiconductor die being coupled to the one or more first package contact pads and the second contact pad of the semiconductor die being coupled to the one or more second package contact pads,
wherein in operation, the semiconductor device causes a current path between the first contact pad and the second contact pad,
wherein the one or more first package contact pads and the one or more second package contact pads are arranged on the first major surface of the semiconductor package to provide multiple non-parallel current paths between the one or more first package contact pads and the one or more second package contact pads,
wherein each of the first and second package contact pads are rectangular shaped pads with a planar outer surface that is exposed from the dielectric layer and is parallel to the first major surface of the semiconductor package
wherein the multiple non-parallel current paths comprise at least two current paths that are not-antiparallel to one another.

2. The semiconductor package of claim 1 , wherein the one or more first package contact pads are arranged laterally adjacent three or more sides of a second package contact pad of the one or more second package contact pads, or wherein the one or more second package contact pads are arranged laterally adjacent three or more sides of a first package contact pad of the one or more first package contact pads.

3. The semiconductor package of claim 1 , wherein the one or more second package contact pads are arranged at two peripheral edges of a footprint that are mutually perpendicular, or wherein the one or more second package contact pads are arranged at three or four peripheral edges of the footprint, wherein the footprint is an arrangement of the first and second contact pads at the first major surface.

4. The semiconductor package of claim 1 , further comprising through package vias arranged at two peripheral edges of a footprint that are mutually perpendicular, or arranged at three or four peripheral edges of the footprint, wherein the footprint is an arrangement of the first and second contact pads at the first major surface.

5. The semiconductor package of claim 1 , further comprising a redistribution structure, wherein a lateral portion of the redistribution structure comprises a lateral layer coupled to the second contact pad, and wherein a vertical portion of the redistribution structure comprises one or more through package vias extending between the lateral layer and the one or more second package contact pads.

6. The semiconductor package of claim 5 , wherein the one or more through package vias are arranged adjacent and substantially parallel to side faces of the semiconductor die.

7. The semiconductor package of claim 5 , wherein the second contact pad has a lateral axis that is perpendicular to the direction of current flow within the semiconductor device, and wherein the one or more through package vias are arranged with respect to edges of the semiconductor die such that a current path is formed in the lateral layer at an angle α with respect to the lateral axis such that 0≤α<90°.

8. The semiconductor package of claim 5 , wherein the one or more through package vias are arranged with respect to edges of the second contact pad such that an effective cross-sectional area of the lateral current path from the second contact pad to the one or more second package pads is greater than a thickness of the lateral layer multiplied by a width of the lateral layer.

9. The semiconductor package of claim 5 , further comprising a plurality of second vias extending between the second contact pad and the lateral layer.

10. The semiconductor package of claim 1 , further comprising a plurality of first vias extending between the first contact pad and the one or more first package contact pads.

11. The semiconductor package of claim 1 , wherein the semiconductor device is a transistor device.

12. A semiconductor package, comprising:
a semiconductor die comprising a semiconductor device, a first contact pad arranged on a first surface of the semiconductor die, and a second contact pad arranged on a second surface of the semiconductor die that opposes the first surface, the semiconductor die being embedded in a dielectric layer;
a package footprint arranged on a first major surface of the semiconductor package, the package footprint comprising one or more first package contact pads and one or more second package contact pads, the first contact pad of the semiconductor die being coupled to the one or more first package contact pads and the second contact pad of the semiconductor die being coupled to the one or more second package contact pads;
a plurality of first vias extending from the first contact pad to the one or more first package contact pads; and
a redistribution structure coupling the second contact pad to at least one second package pad of the one or more second package contact pads arranged on an opposing side of the semiconductor die,
wherein the redistribution structure comprises a lateral layer, a plurality of second vias extending between the second contact pad and the lateral layer, and one or more package vias arranged adjacent opposing side faces of the semiconductor die,
wherein in operation, the semiconductor device causes a current to flow between the first contact pad and the second contact pad,
wherein the current is laterally distributed and flows in the lateral layer of the redistribution structure between the second contact pad and the through package vias in multiple non-parallel directions,
wherein each of the first and second package contact pads are rectangular shaped pads with a planar outer surface that is exposed from the dielectric layer and is parallel to the first major surface of the semiconductor package
wherein at least two of the multiple non-parallel directions are not antiparallel to one another.

13. The semiconductor package of claim 12 , wherein the semiconductor device is a transistor device.

14. A method of fabricating a semiconductor package with a lower package resistance, the method comprising:
defining an area of a package footprint of a semiconductor package comprising a semiconductor die comprising a semiconductor device, a first contact pad arranged on a first surface of the semiconductor die, and a second contact pad arranged on a second surface of the semiconductor die that opposes the first surface, wherein the semiconductor die is embedded in a dielectric layer, wherein the package footprint is arranged on a first major surface of the semiconductor package, wherein the package footprint comprises one or more first package contact pads and one or more second package contact pads, wherein in operation, the semiconductor device causes a current to flow between the first contact pad and the second contact pad;
coupling the first contact pad of the semiconductor die to the one or more first package contact pads;
coupling the second contact pad of the semiconductor die to the one or more second package contact pads by a redistribution structure having a lateral portion and a vertical portion;

Assignees

• Infineon Technologies Austria Ag

Inventors

• Yuferev Sergey
• Fehler Robert
• Palm Petteri

Classifications

• H10W72/9413

  on encapsulations · CPC title

• H10W70/093

  Connecting or disconnecting other interconnections thereto or therefrom, e.g. connecting bond wires or bumps · CPC title

• H10W70/60 Primary

  Insulating or insulated package substrates; Interposers; Redistribution layers (leadframes H10W70/40) · CPC title

• H10W74/111

  the semiconductor body being completely enclosed · CPC title

• H10W72/926

  Multiple bond pads having different sizes · CPC title