Space efficient and low parasitic half bridge

Patent metadata

Field	Value
Publication number	US-11469164-B2
Application number	US-202016744967-A
Country	US
Kind code	B2
Filing date	Jan 16, 2020
Priority date	Jan 16, 2020
Publication date	Oct 11, 2022
Grant date	Oct 11, 2022

Abstract

A packaged half-bridge circuit includes a carrier having a dielectric core and a first layer of metallization formed on an upper surface of the carrier, first and second semiconductor chips, each including a first terminal, a second terminal, and a control terminal, and a conductive connector mounted on the upper surface of the carrier and electrically connected to the first layer of metallization. The first semiconductor chip is configured as a high-side switch of the half-bridge circuit. The second semiconductor chip is configured as a low-side switch of the half-bridge circuit. At least one of the first and second semiconductor chips is embedded within the dielectric core of the carrier. The conductive connector is electrically connected to one of the first and second terminals from one or both of the first and second semiconductor chips.

First claim

The invention claimed is:

1. A half-bridge circuit, comprising:
a carrier comprising a dielectric core and a first layer of metallization formed on an upper surface of the carrier;
first and second semiconductor chips, each comprising a first terminal, a second terminal, and a control terminal; and
a conductive connector mounted on the upper surface of the carrier and electrically connected to the first layer of metallization;
wherein the first semiconductor chip is configured as a high-side switch of the half-bridge circuit,
wherein the second semiconductor chip is configured as a low-side switch of the half-bridge circuit,
wherein at least one of the first and second semiconductor chips is embedded within the dielectric core of the carrier, and
wherein the conductive connector is electrically connected to one of the first and second terminals from one or both of the first and second semiconductor chips,
wherein the second semiconductor chip is embedded within the dielectric core of the carrier, wherein the first terminal of the second semiconductor chip is disposed on a rear surface of the second semiconductor chip which faces the upper surface of the carrier, and wherein first terminal of the second semiconductor chip is electrically connected to a first bond pad that is formed in the first layer of metallization, and
wherein the first terminal of the first semiconductor chip is disposed on a rear surface of the first semiconductor chip which faces away from the upper surface of the carrier, wherein the conductive connector is electrically connected to the first terminal of the first semiconductor chip and to a second bond pad that is formed in the first layer of metallization, and wherein the second bond pad is configured as a power terminal of the half-bridge circuit.

2. The half-bridge circuit of claim 1 , wherein the half bridge circuit further comprises a driver chip that is electrically connected to the control terminals of the first and second semiconductor chips, and wherein the driver chip is disposed on or within the carrier.

3. The half-bridge circuit of claim 2 , wherein the driver chip is mounted on the upper surface of the carrier.

4. The half-bridge circuit of claim 2 , wherein the driver chip is embedded within the dielectric core of the carrier.

5. The half-bridge circuit of claim 1 , wherein the half bridge circuit further comprises a passive electrical component that is electrically connected to one or both of the high-side and the low-side switches, and wherein the passive electrical component is disposed on or within the carrier.

6. The half-bridge circuit of claim 1 , wherein the first terminal of the first semiconductor chip is disposed on a rear surface of the first semiconductor chip which faces away from the upper surface of the carrier, wherein the conductive connector is electrically connected to the first terminal of the first semiconductor chip and to a second bond pad that is formed in the first layer of metallization, and wherein the second bond pad is configured as a power terminal of the half-bridge circuit.

7. The half-bridge circuit of claim 6 , wherein the conductive connector is a metal clip that is affixed to the first semiconductor chip and to the second bond pad by a conductive adhesive material.

8. The half-bridge circuit of claim 7 , wherein the carrier further comprises third and fourth bonds that are each formed in the first layer of metallization, wherein the third and fourth bond pads are each configured as a power terminal of the half-bridge circuit, wherein the metal clip comprises a first wing that extends across a first edge side of the first semiconductor chip and reaches the second bond pad, a second wing that extends across a second edge side of the first semiconductor chip and reaches the third bond pad, and a third wing that extends across a third edge side of the first semiconductor chip and reaches the fourth bond pad.

9. The half-bridge circuit of claim 6 , further comprising an electrically insulating encapsulant body that is formed on the upper surface of the carrier, wherein the encapsulant body encapsulates the first semiconductor chip, and wherein an upper surface of the metal clip is exposed from an upper surface of the encapsulant body.

10. The half-bridge circuit of claim 9 , wherein the first semiconductor chip and the conductive connector are integral components of a discrete packaged semiconductor device that is mounted on the upper surface of the carrier, wherein the conductive connector is a lead frame of the discrete packaged semiconductor device, wherein the discrete packaged semiconductor device is arranged with the first semiconductor chip disposed between the lead frame and the carrier, and wherein the lead frame extends to and electrically contacts the second bond pad.

11. The half-bridge circuit of claim 9 , further comprising an electrically insulating encapsulant body that is formed on the upper surface of the carrier, wherein the encapsulant body encapsulates the discrete packaged semiconductor device, and wherein an upper surface of the lead frame is exposed from an upper surface of the encapsulant body.

12. The half-bridge circuit of claim 1 , wherein the first semiconductor chip is embedded within the dielectric core of the carrier, wherein the second terminal of the first semiconductor chip is disposed on a main surface of the second semiconductor chip which faces the upper surface of the carrier, and wherein the conductive connector electrically connects the second terminal of the first semiconductor chip to the first terminal of the second semiconductor chip.

13. The half-bridge circuit of claim 12 , wherein the conductive connector is a metal clip that is affixed to the first semiconductor chip and to the second bond pad by a conductive adhesive material, wherein the metal clip is part of a conductive connection that current must flow through when flowing between the second terminal of the first semiconductor chip device and the first terminal of the second semiconductor chip.

14. A method of producing a half-bridge circuit, the method comprising:
providing a carrier comprising a dielectric core and a first layer of metallization formed on an upper surface of the carrier;
providing first and second semiconductor chips, each comprising a first terminal, a second terminal, and a control terminal;
mounting a conductive connector on the upper surface of the carrier and electrically connecting the connective connector to the first layer of metallization;
embedding the second semiconductor chip within the dielectric core of the carrier such that a rear surface of the second semiconductor chip that comprises the first terminal of the second semiconductor chip faces the upper surface of the carrier;
mounting the first semiconductor chip on the upper surface of the carrier such that a rear surface of the first semiconductor chip that comprises the first terminal faces away from the upper surface of the carrier; and
electrically connecting the first terminal of the first semiconductor chip to a second bond pad that is formed in the first layer of metallization with the conductive connector,
wherein the first semiconductor chip is configured as a high-side switch of the half-bridge circuit,
wherein the second semiconductor chip is configured as a low-side switch of the half-bridge circuit,
wherein at least one of the first and second semiconductor chips is embedded within the dielectric core of the carrier, and
wherein the conductive connector is electrically connected to one of the first and second terminals from one or both of the first and second s

Assignees

• Infineon Technologies Ag

Inventors

• Fehler Robert
• Cho Eung San
• Clavette Danny
• Palm Petteri

Classifications

• H10W72/926

  Multiple bond pads having different sizes · CPC title

• H10W90/00 Primary

  Package configurations · CPC title

• H10W72/076

  of strap connectors · CPC title

• H10W72/60

  Strap connectors, e.g. thick copper clips for grounding of power devices · CPC title

• H10W70/481

  for devices being provided for in groups H10D8/00 - H10D48/00 · CPC title