Semiconductor package and passive element with interposer

Patent metadata

Field	Value
Publication number	US-11848262-B2
Application number	US-202117176678-A
Country	US
Kind code	B2
Filing date	Feb 16, 2021
Priority date	Feb 16, 2021
Publication date	Dec 19, 2023
Grant date	Dec 19, 2023

Abstract

A semiconductor assembly includes an interposer that includes an insulating substrate, a plurality of upper contact pads on an upper surface of the substrate, and a plurality of lower contact pads on a lower surface of the substrate, a semiconductor package that includes a semiconductor die embedded within a package body and a plurality of package terminals exposed from the package body, a first passive electrical element that includes first and second terminals, a first electrical connection between the first terminal of the first passive electrical element and a first one of the lower contact pads via the interposer, a second electrical connection between the second terminal of the first passive electrical element and a first one of the package terminals, and a third electrical connection between a second one of the package terminals and a second one of the lower contact pads via the interposer.

First claim

The invention claimed is:

1. A semiconductor assembly, comprising:
an interposer that comprises an electrically insulating substrate, a plurality of upper contact pads disposed on an upper surface of the substrate, and a plurality of lower contact pads disposed on a lower surface of the substrate that is opposite from the upper surface;
a semiconductor package that comprises a semiconductor die embedded within a package body and a plurality of package terminals that are exposed from the package body;
a first passive electrical element that comprises first and second terminals;
a first electrical connection between the first terminal of the first passive electrical element and a first one of the lower contact pads via the interposer;
a second electrical connection between the second terminal of the first passive electrical element and a first one of the package terminals; and
a third electrical connection between a second one of the package terminals and a second one of the lower contact pads via the interposer.

2. The semiconductor assembly of claim 1 , wherein the semiconductor package is mounted on the interposer such that the package terminals face and electrically connect with a group of the upper contact pads.

3. The semiconductor assembly of claim 1 , wherein the first passive electrical element is a discrete passive electrical element that is disposed over and overlaps with the semiconductor package.

4. The semiconductor assembly of claim 3 , wherein the first electrical connection comprises a first conductive connector that vertically extends between a first one of the upper contact pads and a lower surface of the first passive electrical element, and wherein the first one of the upper contact pads is electrically connected to the first one of the lower contact pads via the interposer.

5. The semiconductor assembly of claim 4 , wherein the second electrical connection comprises a second conductive connector that vertically extends between a second one of the upper contact pads and the lower surface of the first passive electrical element, and wherein the second one of the upper contact pads is electrically connected to the first one of the package terminals via the interposer.

6. The semiconductor assembly of claim 4 , wherein the first one of the package terminals is disposed on an upper side of the semiconductor package that faces away from the interposer.

7. The semiconductor assembly of claim 6 , wherein the semiconductor package comprises first and second outer edge sides that are opposite to one another, wherein the first one of the package terminals is disposed closer to the second outer edge side, and wherein the first outer edge side faces the first conductive connector.

8. The semiconductor assembly of claim 6 , wherein the semiconductor package comprises first and second outer edge sides that are opposite to one another, wherein the first one of the package terminals is disposed closer to the second outer edge side, and wherein the second outer edge side faces the first conductive connector.

9. The semiconductor assembly of claim 6 , wherein the second electrical connection comprises a second conductive connector that vertically extends between a second one of the upper contact pads and the lower surface of the first passive electrical element, and wherein the second one of the upper contact pads is electrically connected to the first one of the package terminals by a first conductive clip that is disposed outside of the semiconductor package.

10. The semiconductor assembly of claim 6 , wherein the second electrical connection comprises a second conductive connector that directly contacts the first one of the package terminals, and wherein the second conductive connector comprises a lateral section that extends across a first outer edge side of the semiconductor package and a vertical section that extends from the lateral section to the lower surface of the first passive electrical element.

11. The semiconductor assembly of claim 3 , further comprising a second passive electrical element that is mounted on an upper surface of the semiconductor package, and wherein the first passive electrical element is disposed over and spaced apart from the second passive electrical element.

12. The semiconductor assembly of claim 1 , wherein the first passive electrical element is integrally formed in the interposer.

13. The semiconductor assembly of claim 1 , wherein the semiconductor package comprises a pair of power switching devices which form the high-side switch and low-side switch of a half-bridge circuit and a driver die configured to control the power switching devices, and wherein the first passive electrical element is an inductor that is connected in series between an output of the half-bridge circuit and the circuit carrier.

14. The semiconductor assembly of claim 1 , wherein the semiconductor package comprises a conductive metal clip disposed on an upper surface of the semiconductor package that is opposite from the interposer, and wherein the conductive metal clip forms an electrical interconnection between two terminals of the semiconductor package.

15. A semiconductor assembly, comprising:
a circuit carrier that comprises an electrically insulating substrate and a plurality of bond pads disposed on a main surface of the circuit carrier;
an interposer that comprises an electrically insulating substrate, a plurality of upper contact pads disposed on an upper surface of the substrate, and a plurality of lower contact pads disposed on a lower surface of the substrate that is opposite from the upper surface;
a semiconductor package that comprises a semiconductor die embedded within a package body and a plurality of package terminals that are exposed from the package body; and
a first passive electrical element;
wherein the interposer is mounted on the circuit carrier with the lower contact pads facing and electrically connected to the bond pads,
wherein the semiconductor package is mounted on the interposer with the package terminals facing and electrically connected to the upper contact pads, and
wherein the semiconductor package and the first passive electrical element are each electrically connected to the circuit carrier via the interposer.

16. The semiconductor assembly of claim 15 , wherein the first passive electrical element is a discrete passive electrical element that is disposed over and overlaps with the semiconductor package.

17. The semiconductor assembly of claim 15 , wherein the first passive electrical element comprises first and second terminals, wherein the first terminal is electrically connected to the circuit carrier via the interposer, and wherein the second terminal is electrically connected to a first one of the package terminals.

Assignees

• Infineon Technologies Ag

Inventors

• Kessler Angela
• Carroll Robert
• Fehler Robert

Classifications

• H10W90/724

  between a chip and a stacked insulating package substrate, interposer or RDL · CPC title

• H10W90/00 Primary

  Package configurations · CPC title

• H10W70/093

  Connecting or disconnecting other interconnections thereto or therefrom, e.g. connecting bond wires or bumps · CPC title

• H10W70/685

  comprising multiple insulating layers · CPC title

• H10W70/65

  Shapes or dispositions of interconnections · CPC title