Circuitry and method of forming a circuitry

Patent metadata

Field	Value
Publication number	US-11935874-B2
Application number	US-202117384217-A
Country	US
Kind code	B2
Filing date	Jul 23, 2021
Priority date	Jul 24, 2020
Publication date	Mar 19, 2024
Grant date	Mar 19, 2024

Abstract

A circuitry is provided. The circuitry may include a power stage including a first transistor and a second transistor, an encapsulation including encapsulation material encapsulating the power stage, wherein the first transistor and the second transistor are arranged in an L-shape with respect to each other along their long axes, and a passive electronic component arranged on or embedded within the encapsulation at least partially, in top view, within a rectangular area defined by the L-shape configuration and further next to the first transistor and next to the second transistor.

First claim

What is claimed is:

1. A circuitry comprising:
a power stage comprising a first transistor and a second transistor;
an encapsulation comprising encapsulation material encapsulating the power stage;
wherein the first transistor and the second transistor are arranged in an L-shape with respect to each other along their long axes,
a passive electronic component arranged on or embedded within the encapsulation at least partially, in top view, within a rectangular area defined by the L-shape configuration and further next to the first transistor and next to the second transistor,
wherein the passive electronic component is completely arranged in the rectangular area.

2. The circuitry of claim 1 ,
wherein the passive electronic component is arranged in an orientation angle in the range from about 45° to about 135°, wherein the orientation angle is an angle between a symmetry line along the short edge of the passive component and a connection line crossing a top view center of the first transistor and a top view center of the second transistor.

3. A circuitry comprising:
a power stage comprising a first transistor and a second transistor;
encapsulation comprising encapsulation material encapsulating the power stage;
wherein the first transistor and the second transistor are arranged in an L-shape with respect to each other along their long axes,
a passive electronic component arranged on or embedded within the encapsulation in an orientation angle in the range from about 45° to about 135° , wherein the orientation angle is an angle between a symmetry line along the short edge of the passive component and a connection line crossing a top view center of the first transistor and a top view center of the second transistor,
wherein the passive electronic component is arranged, in top view, completely within a rectangular area defined by the L-shape configuration and further next to the first transistor and next to the second transistor.

4. The circuitry of claim 3 ,
wherein the rectangular area is defined as follows:
in a first direction, the rectangle is adjacent to an inner edge of the first transistor and has a length of a third of the long axis of the second transistor; and
in a second direction orthogonal to the first direction, the rectangle is adjacent to an inner edge of the second transistor and has a length of a sum of a separation between the first transistor and the second transistor and either a third of the long axis of the second transistor or half of the long axis of the first transistor, whatever is larger.

5. The circuitry of claim 4 ,
wherein the passive electronic component is at least partially arranged in a triangular area defined by the L-shape configuration and a line connecting an end of an inner edge of the first transistor that is furthest away from the second transistor and an end of an inner edge of the second transistor that is furthest away from the first transistor.

6. The circuitry of claim 5 ,
wherein the passive electronic component is completely arranged in the triangular area.

7. The circuitry of claim 6 ,
wherein the passive electronic component is a capacitor.

8. The circuitry of claim 7 ,
wherein the power stage comprises a half-bridge circuit;
wherein the first transistor is a high side transistor of the half-bridge circuit; and
wherein the second transistor is a low side transistor of the half-bridge circuit.

9. The circuitry of claim 8 ,
wherein the passive electronic component is electrically connected between a drain of the high side transistor and a source of the low side transistor.

10. The circuitry of any of claim 9 ,
wherein the first transistor and the second transistor are arranged by chip embedding technology.

11. The circuitry of claim 10 , further comprising:
a driver circuit,
wherein the passive electronic component is arranged laterally between the second transistor and the driver circuit in top view.

12. The circuitry of any of claim 11 ,
wherein a first transistor area covered by the first transistor is smaller than a second transistor area covered by the second transistor.

Assignees

• Infineon Technologies Ag

Inventors

• Fehler Robert
• Yuferev Sergey

Classifications

• H10W74/111

  the semiconductor body being completely enclosed · CPC title

• H10W74/01

  Manufacture or treatment · CPC title

• H10W44/601 Primary

  Capacitive arrangements (H10W44/20 takes precedence) · CPC title

• H10W72/944

  Dispositions of multiple bond pads · CPC title

• H10W72/9413

  on encapsulations · CPC title