Semiconductor devices including parallel electrically conductive layers

Patent metadata

Field	Value
Publication number	US-2021287964-A1
Application number	US-202117196652-A
Country	US
Kind code	A1
Filing date	Mar 9, 2021
Priority date	Mar 10, 2020
Publication date	Sep 16, 2021
Grant date	—

Abstract

A semiconductor device is disclosed. In one example, the semiconductor device includes a semiconductor chip including a first chip contact pad on a first chip main surface. The semiconductor device further includes a first electrically conductive layer arranged over the first chip main surface and electrically coupled to the first chip contact pad, wherein the first electrically conductive layer extends in a direction parallel to the first chip main surface. An electrical through connection is electrically coupled to the first electrically conductive layer and to a second electrically conductive layer, wherein the electrical through connection extends in a direction perpendicular to the first chip main surface, and wherein, in a top view of the first chip main surface, the electrical through connection and the semiconductor chip are non-overlapping.

First claim

1 . A semiconductor device, comprising:
a semiconductor chip comprising a first chip contact pad on a first chip main surface; a first electrically conductive layer arranged over the first chip main surface and electrically coupled to the first chip contact pad, wherein the first electrically conductive layer extends in a direction parallel to the first chip main surface; a second electrically conductive layer arranged over the first electrically conductive layer and electrically coupled to the first electrically conductive layer, wherein the second electrically conductive layer extends in a direction parallel to the first electrically conductive layer; and an electrical through connection electrically coupled to the first electrically conductive layer and to the second electrically conductive layer, wherein the electrical through connection extends in a direction perpendicular to the first chip main surface, and wherein, in a top view of the first chip main surface, the electrical through connection and the semiconductor chip are non-overlapping.

2 . The semiconductor device of claim 1 , wherein the first electrically conductive layer and the second electrically conductive layer are configured to carry an electrical current in parallel between the first chip contact pad and the electrical through connection.

3 . The semiconductor device of claim 1 , wherein the semiconductor chip comprises a power transistor and the first chip contact pad comprises a drain contact pad of the power transistor.

4 . The semiconductor device of claim 1 , further comprising:
a first device main surface, wherein the first chip main surface faces the first device main surface; and a second device main surface arranged opposite to the first device main surface, wherein the electrical through connection is electrically coupled to a first device contact pad arranged at the second device main surface.

5 . The semiconductor device of claim 4 , wherein, in a top view of the first chip main surface, the semiconductor chip and the first device contact pad at least partly overlap.

6 . The semiconductor device of claim 1 , further comprising:
a laminate, wherein at least the semiconductor chip, the first electrically conductive layer and the electrical through connection are embedded in the laminate.

7 . The semiconductor device of claim 1 , wherein a surface of the second electrically conductive layer facing away from the first chip main surface is exposed.

8 . The semiconductor device of claim 1 , wherein, in a top view of the first chip main surface, the first electrically conductive layer covers more than 50 percent of the first chip main surface.

9 . The semiconductor device of claim 1 , wherein, in a direction perpendicular to the first chip main surface, a thickness of the first electrically conductive layer is smaller than a thickness of the second electrically conductive layer.

10 . The semiconductor device of claim 1 , wherein, in a direction perpendicular to the first chip main surface, a thickness of the first electrically conductive layer lies in a range from 15 micrometer to 45 micrometer.

11 . The semiconductor device of claim 1 , wherein, in a direction perpendicular to the first chip main surface, a thickness of the second electrically conductive layer lies in a range from 30 micrometer to 90 micrometer.

12 . The semiconductor device of claim 1 , further comprising:
a first via array electrically coupling the first chip contact pad and the first electrically conductive layer.

13 . The semiconductor device of claim 11 , wherein the first via array covers more than 5 percent of the first chip contact pad.

14 . The semiconductor device of claim 11 , wherein a minimum distance between the first via array and an edge of the semiconductor chip lies in a range from about 50 micrometers to about 350 micrometers.

15 . The semiconductor device of claim 1 , further comprising:
a second via array electrically coupling the first electrically conductive layer and the second electrically conductive layer.

16 . The semiconductor device of claim 14 , wherein, in a top view of the first chip main surface, via connections of the first via array and via connections of the second via array are arranged congruently.

17 . The semiconductor device of claim 1 , further comprising:
a second chip contact pad arranged on a second chip main surface opposite to the first chip main surface; and a third electrically conductive layer arranged over the second chip main surface and electrically coupled to the second chip contact pad, wherein the third electrically conductive layer extends in a direction parallel to the second chip main surface.

18 . The semiconductor device of claim 16 , further comprising:
a third via array electrically coupling the second chip contact pad and the third electrically conductive layer.

19 . The semiconductor device of claim 16 , further comprising:
a second device contact pad arranged at the second device main surface; and a fourth via array electrically coupling the third electrically conductive layer and the second device contact pad.

20 . The semiconductor device of claim 18 , wherein, in a top view of the first chip main surface, via connections of the third via array and via connections of the fourth via array are arranged congruently.

21 . Method for manufacturing a semiconductor device, wherein the method comprises:
providing a semiconductor chip comprising a first chip contact pad on a first chip main surface; forming a first electrically conductive layer arranged over the first chip main surface and electrically coupled to the first chip contact pad, wherein the first electrically conductive layer extends in a direction parallel to the first chip main surface; forming a second electrically conductive layer arranged over the first electrically conductive layer and electrically coupled to the first electrically conductive layer, wherein the second electrically conductive layer extends in a direction parallel to the first electrically conductive layer; and forming an electrical through connection electrically coupled to the first electrically conductive layer and to the second electrically conductive layer, wherein the electrical through connection extends in a direction perpendicular to the first chip main surface, and wherein, in a top view of the first chip main surface, the electrical through connection and the semiconductor chip are non-overlapping.

Assignees

• Infineon Technologies Ag

Inventors

• Palm Petteri
• Fehler Robert
• Hoeglauer Josef
• Kessler Angela

Classifications

• H10W20/481

  on the rear surfaces of the wafers or substrates · CPC title

• H10W72/926

  Multiple bond pads having different sizes · CPC title

• H10W72/944

  Dispositions of multiple bond pads · CPC title

• H10W72/9413

  on encapsulations · CPC title

• H10W72/0198

  batch processes · CPC title