Input/output pins for chip-embedded substrate
US-2018122745-A1 · May 3, 2018 · US
US12009290B2 · US · B2
| Field | Value |
|---|---|
| Publication number | US-12009290-B2 |
| Application number | US-202318135771-A |
| Country | US |
| Kind code | B2 |
| Filing date | Apr 18, 2023 |
| Priority date | Oct 7, 2020 |
| Publication date | Jun 11, 2024 |
| Grant date | Jun 11, 2024 |
A practical reading order for non-experts. Skip the full description unless you need deep technical detail.
What the patent document calls the invention.
A short plain-language summary of the technical disclosure.
Who owns or filed the patent and who is credited as inventor.
Filing, priority, publication, and grant dates set the timeline.
The legal scope of protection — read this for what is actually claimed.
Technology tags used to group this patent with similar filings.
Prior art links and similar publications in this corpus.
Official abstract text for this publication.
A semiconductor module is provided that includes a low side switch, a high side switch and a control chip. The low side switch and the high side switch are arranged laterally adjacent one another and coupled by a switch node connector to form a half bridge circuit. The switch node connector includes two or more branches that have an arrangement with respect to the low side switch and to the high side switch and that each have a cross-sectional area.
Opening claim text (preview).
What is claimed is: 1. A semiconductor module, comprising: a low side switch; a high side switch; and a control chip; wherein the low side switch and the high side switch are arranged laterally adjacent one another and coupled by a switch node connector to form a half bridge circuit, wherein the switch node connector comprises two or more branches that have an arrangement with respect to the low side switch and to the high side switch and that each have a cross-sectional area. 2. The semiconductor module of claim 1 , wherein the switch node connector comprises a first portion that is arranged on the low side switch, a second portion that is arranged on the high side switch, wherein the two or more branches extend between the first portion and the second portion, and wherein the two or more branches are spaced apart from one another. 3. The semiconductor module of claim 1 , wherein a second branch of the two or more branches has a cross-sectional area that is smaller than a cross-sectional area of a first branch of the two or more branches. 4. The semiconductor module of claim 1 , wherein the switch node connector extends between a drain pad of the low side switch and a source pad of the high side switch, and wherein the two or more branches are positioned between the drain pad of the low side switch and the source pad of the high side switch. 5. The semiconductor module of claim 1 , wherein the switch node connector has a form of a conductive layer that comprises at least one aperture to form a first branch and a second branch that are physically spaced apart from one another. 6. The semiconductor module of claim 5 , wherein the at least one aperture is positioned at least in part above the control chip. 7. The semiconductor module of claim 5 , wherein the first and second branches extend around opposing sides of the control chip. 8. The semiconductor module of claim 1 , wherein the switch node connector has a form of a contact clip that comprises at least one aperture to form a first branch and a second branch that are physically spaced apart from one another. 9. The semiconductor module of claim 8 , wherein the at least one aperture is positioned at least in part above the control chip. 10. The semiconductor module of claim 8 , wherein the first and second branches extend around opposing sides of the control chip. 11. The semiconductor module of claim 1 , wherein the low side switch and the high side switch each have a substantially cuboid form and are arranged laterally adjacent one another in a L-shape. 12. The semiconductor module of claim 1 , wherein the two or more branches are formed in a single layer. 13. The semiconductor module of claim 1 , wherein the control chip comprises gate driver circuitry and is coupled to a gate of the low side switch and a gate of the high side switch. 14. The semiconductor module of claim 1 , wherein the semiconductor module has a footprint comprising a V high pad, a V low pad, a switch node pad and one or more logic pads, and wherein the switch node connector is coupled to the switch node pad of the semiconductor module. 15. The semiconductor module of claim 14 , wherein the low side switch and the high side switch are coupled in series between the V low pad and the V high pad of the semiconductor module by the switch node connector, and wherein the switch node connector is positioned within the semiconductor module. 16. The semiconductor module of claim 14 , wherein the low side switch comprises a source pad on a first side that faces towards the V low pad and a drain pad on a second side opposing the first side, wherein the drain pad is connected to the switch node connector, wherein the high side switch comprises a source pad on a first side and a drain pad on a second side opposing the first side, wherein the drain pad of the high side switch faces towards the V high pad and the source pad is connected to the switch node connector. 17. The semiconductor module of claim 1 , wherein the low side switch and the high side switch are each provided by a vertical transistor device. 18. The semiconductor module of claim 1 , wherein a second branch of the two or more branches has a length that is greater than a length of a first branch of the two or more branches. 19. The semiconductor module of claim 1 , wherein the two or more branches extend in at least two layers that are connected by one or more conductive connections. 20. The semiconductor module of claim 1 , wherein the two or more branches each provide a route for carrying current between the low side switch and the high side switch.
Package configurations · CPC title
for connecting multiple chips together · CPC title
Shapes or dispositions of interconnections · CPC title
Multiple chips on leadframes · CPC title
for devices being provided for in groups H10D8/00 - H10D48/00 · CPC title
Related publications grouped by family.
Answers are generated from the same data shown on this page.