Semiconductor package and method of manufacturing a semiconductor package

Patent metadata

Field	Value
Publication number	US-11444017-B2
Application number	US-201916560139-A
Country	US
Kind code	B2
Filing date	Sep 4, 2019
Priority date	Sep 5, 2018
Publication date	Sep 13, 2022
Grant date	Sep 13, 2022

Abstract

In an embodiment, a semiconductor package includes a semiconductor device embedded in an insulating layer, a contact pad having an area, and a vertical redistribution structure including substantially parallel vertical paths arranged in the insulating layer and extending perpendicular to the area of the contact pad. The substantially vertical paths are non-uniformly distributed over the area of the contact pad.

First claim

What is claimed is:

1. A semiconductor package, comprising:
a semiconductor device embedded in an insulating layer;
a contact pad having an area that does not overlap the semiconductor device, and
a vertical current redistribution structure comprising substantially parallel vertical current paths arranged in the insulating layer and extending perpendicular to the area of the contact pad that does not overlap the semiconductor device, the substantially parallel vertical current paths being non-uniformly distributed over the area of the contact pad that does not overlap the semiconductor device.

2. The semiconductor package of claim 1 , wherein the substantially parallel vertical current paths are arranged in a L-shape, U shape or O-shape on the contact pad.

3. The semiconductor package of claim 1 , further comprising a plurality of via sites forming a two-dimensional array of a first pitch on the area of the contact pad that does not overlap the semiconductor device, wherein the substantially parallel vertical current paths comprise conductive vias extending through the insulating layer and located at a subset of the via sites such that the two-dimensional array includes at least one via-free zone in the two-dimensional array.

4. The semiconductor package of claim 3 , wherein the at least one via-free zone has a lateral shape such that the conductive vias are arranged in a L-shape, U shape, O-shape on the area.

5. The semiconductor package of claim 3 , wherein the via sites are arranged in off-set rows or in rows and columns.

6. The semiconductor package of claim 3 , wherein a first contact pad is arranged on a first major surface of the insulating layer and the conductive vias extend between the first contact pad and a lateral conductive layer positioned on a second major surface of the insulating layer, the second major surface opposing the first major surface.

7. The semiconductor package of claim 6 , wherein the conductive vias are positioned adjacent and spaced apart from a side face of the semiconductor device and the at least one via-free zone is located adjacent an outer edge of the insulating layer.

8. The semiconductor package of claim 6 , wherein the first contact pad is arranged on the insulating layer and the conductive vias extend between the first contact pad and a first device contact pad arranged on a first major surface of the semiconductor device.

9. The semiconductor package of claim 6 , wherein the first contact pad is arranged on the semiconductor device and the conductive vias extend between the first contact pad and the lateral conductive layer positioned on the second major surface of the insulating layer.

10. The semiconductor package of claim 3 , further comprising:
a device contact pad on a major surface of the semiconductor device, the device contact pad having a second area, a set of second via sites forming a two-dimensional array of a second pitch on the second area; and
conductive vias extending through the insulating layer and located at a subset of the second via sites and such that the two-dimensional array includes at least one via-free zone in the two-dimensional array, the conductive vias extending between the device contact pad and a lateral conductive layer.

Assignees

• Infineon Technologies Austria Ag

Inventors

• Yuferev Sergey
• Fehler Robert
• Palm Petteri

Classifications

• H10W72/944

  Dispositions of multiple bond pads · CPC title

• H10W72/019

  of bond pads · CPC title

• H10W20/435

  Cross-sectional shapes or dispositions of interconnections · CPC title

• H10W20/081

  by forming openings in the dielectric parts · CPC title

• H10W20/056

  by filling conductive material into holes, grooves or trenches · CPC title