SRAM with burst mode operation
US-11527282-B2 · Dec 13, 2022 · US
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Chaba Ritu patents
Chaba Ritu is listed as an inventor on 24 patents in our database. Major assignees and classification codes are summarized below.
| Metric | Value |
|---|---|
| Inventor | Chaba Ritu |
| Total patents | 24 |
| First publication | Jan 6, 2015 |
| Latest publication | Dec 13, 2022 |
Notable patents
Publications ranked by popularity score, then publication date.
Sram with burst mode operation
US-2021134358-A1 · May 6, 2021 · US
SRAM with burst mode operation
US-10923185-B2 · Feb 16, 2021 · US
Sram with burst mode operation
US-2020388328-A1 · Dec 10, 2020 · US
Memory hold margin characterization and correction circuit
US-10622044-B2 · Apr 14, 2020 · US
Intelligent bit line precharge for improved dynamic power
US-10290345-B2 · May 14, 2019 · US
Memory hold margin characterization and correction circuit
US-2019096460-A1 · Mar 28, 2019 · US
Dual sensing current latched sense amplifier
US-10242720-B2 · Mar 26, 2019 · US
Metal layers for a three-port bit cell
US-2019035796-A1 · Jan 31, 2019 · US
Metal layers for a three-port bit cell
US-10141317-B2 · Nov 27, 2018 · US
Recent patents
Latest publications not already listed above.
Reducing leakage current in a memory device
US-9916904-B2 · Mar 13, 2018 · US
Intelligent bit line precharge for improved dynamic power
US-2017278565-A1 · Sep 28, 2017 · US
Metal layers for a three-port bit cell
US-2017062439-A1 · Mar 2, 2017 · US
Metal layers for a three-port bit cell
US-9524972-B2 · Dec 20, 2016 · US
Intelligent bit line precharge for improved dynamic power
US-9514805-B1 · Dec 6, 2016 · US
Metal layers for a three-port bit cell
US-2016240539-A1 · Aug 18, 2016 · US
Word line and bit line tracking across diverse power domains
US-9418716-B1 · Aug 16, 2016 · US
Tracking scheme for floating bitline precharge
US-2015357013-A1 · Dec 10, 2015 · US
Reconfigurable memory interface circuit to support a built-in memory scan chain
US-9188642-B2 · Nov 17, 2015 · US
Weak keeper circuit for memory device
US-9082465-B2 · Jul 14, 2015 · US
Read/write assist for memories
US-9030863-B2 · May 12, 2015 · US
Read/write assist for memories
US-2015085568-A1 · Mar 26, 2015 · US
Reconfigurable memory interface circuit to support a built-in memory scan chain
US-2015058686-A1 · Feb 26, 2015 · US
Memory with multiple word line design
US-8929153-B1 · Jan 6, 2015 · US
Major assignees
Companies most often associated with this inventor's publications.
| Assignee | Patents |
|---|---|
| Qualcomm Inc | 24 |
| Chen Nan | 2 |
| Chaba Ritu | 2 |
| Sani Mehdi Hamidi | 1 |
Top CPC classifications
Most common classification codes across this inventor's patents.
| CPC | Patents |
|---|---|
| G11C11/419 | 17 |
| G11C7/12 | 12 |
| G11C11/418 | 10 |
| G11C8/14 | 8 |
| G11C7/222 | 7 |