Sram with burst mode operation

Patent metadata

Field	Value
Publication number	US-2021134358-A1
Application number	US-202117144077-A
Country	US
Kind code	A1
Filing date	Jan 7, 2021
Priority date	Jun 4, 2019
Publication date	May 6, 2021
Grant date	—

Abstract

A memory is provided that is configured to practice both a conventional normal read operation and also a burst mode read operation. During the normal read operation, the memory pre-charges the bit lines in a group of multiplexed columns. Each column has a sense amplifier that latches a bit decision for the column during the normal read operation. If a subsequent read operation addresses the same group of multiplexed columns, the memory invokes the burst-mode read operation during which the bit lines are not pre-charged.

First claim

What is claimed is:

1 . A burst-mode method for a static random-access memory (SRAM) comprising:
decoding a first address responsive to a first memory clock cycle, wherein the first address identifies a first column in a group of multiplexed columns; asserting a word line responsive to the first memory clock cycle; responsive to the word line assertion: sensing both a first bit from a first bitcell in the first column and a second bit from a second bitcell in a second column in the group of multiplexed columns; latching the first bit in a data output latch responsive to the first memory clock cycle; decoding a second address responsive to a second memory clock cycle, wherein the second address identifies the second bitcell; and latching the second bit in the data output latch responsive to the second memory clock cycle, wherein the word line is not asserted during the second memory clock cycle.

2 . The burst-mode method of claim 1 , wherein sensing the first bit comprises:
while the word line is asserted, initiating a charge-transfer period in which a first charge transfer from a first pre-charged bit line in the first column to a first sense node depends upon a binary value of the first bit; and sensing the first bit responsive to the first charge transfer.

3 . The burst-mode method of claim 2 , further comprising:
discharging the first sense node prior to the charge-transfer period.

4 . The burst-mode method of claim 2 , wherein sensing the first bit comprising latching the first bit in a sense amplifier.

5 . The burst-mode method of claim 3 , wherein the first sense node is not discharged during the second memory clock cycle.

6 . The burst-mode method of claim 1 , further comprising:
sensing a third bit from a third column in the group of multiplexed columns responsive to the word line assertion; decoding a third address responsive to a third memory clock cycle, wherein the third address identifies a third bitcell in the third column; and latching the third bit in the data output latch responsive to the third memory clock cycle, wherein the word line is not asserted during the third memory clock cycle.

Assignees

• Qualcomm Inc

Inventors

• Jung Changho
• Kim Keejong
• Jung Chulmin
• Chaba Ritu

Classifications

• G11C11/418

  Address circuits · CPC title

• G11C7/1021

  Page serial bit line access mode, i.e. using an enabled row address stroke pulse with its associated word line address and a sequence of enabled column address stroke pulses each with its associated bit line address · CPC title

• G11C8/10

  Decoders · CPC title

• G11C7/222

  Clock generating, synchronizing or distributing circuits within memory device · CPC title

• G11C11/419 Primary

  Read-write [R-W] circuits · CPC title