Intelligent bit line precharge for improved dynamic power

Patent metadata

Field	Value
Publication number	US-10290345-B2
Application number	US-201615331704-A
Country	US
Kind code	B2
Filing date	Oct 21, 2016
Priority date	Mar 28, 2016
Publication date	May 14, 2019
Grant date	May 14, 2019

Abstract

A method and apparatus for writing data to a memory device are provided that do not change the precharge states for a bit line pair in a current write cycle if the current data bit is unchanged from the preceding write cycle.

First claim

We claim:

1. A method of write driving a bit line pair, comprising:
discharging a first bit line in the bit line pair while coupling a remaining second bit line in the bit line pair to a power supply node responsive to a first bit to be written through the bit line pair in a first write cycle;
during the first write cycle, while the first bit line is discharged and the second bit line is coupled to the power supply node, coupling the bit line pair to a first bit cell to write the first bit into the first bit cell in the first write cycle; and
in a second write cycle subsequent to the first write cycle, continuing to discharge the first bit line and to couple the second bit line to the power supply node without a precharging of the first bit line responsive to a second bit to be written in the second write cycle equaling the first bit.

2. The method of claim 1 , further comprising coupling the bit line pair to a second bit cell while the first bit line is discharged and the second bit line is coupled to the power supply node to write the second bit into the second bit cell in the second write cycle.

3. The method of claim 1 , further comprising:
in response to an assertion of a data masking signal, coupling both the first bit line and the second bit line to the power supply node.

4. The method of claim 1 , wherein the discharging of the first bit line in the first write cycle occurs during a half cycle of a memory clock signal.

Assignees

• Qualcomm Inc

Inventors

• Pallerla Arun Babu
• Chaba Ritu

Classifications

• G11C7/12

  Bit line control circuits, e.g. drivers, boosters, pull-up circuits, pull-down circuits, precharging circuits, equalising circuits, for bit lines · CPC title

• G11C7/1009

  Data masking during input/output · CPC title

• G11C11/419 Primary

  Read-write [R-W] circuits · CPC title