Dual sensing current latched sense amplifier

Patent metadata

Field	Value
Publication number	US-10242720-B2
Application number	US-73162310-A
Country	US
Kind code	B2
Filing date	Mar 25, 2010
Priority date	Mar 25, 2010
Publication date	Mar 26, 2019
Grant date	Mar 26, 2019

Abstract

A sense amplifier and method thereof are provided. The sense amplifier includes first and second transistors coupled to first and second bit lines, respectively. The first and second transistors are configured to connect the first and second bit lines to a differential amplifier during a first state (e.g., when a differential voltage is present on the first and second bit lines and prior to a sense signal transition) and to isolate the first and second bit lines from the differential amplifier during a second state (e.g., after the sense signal transition). The sense amplifier further includes a third transistor configured to deactivate the differential amplifier during the first state and configured to activate the differential amplifier during the second state.

First claim

What is claimed is:

1. An apparatus comprising:
a current latched sense amplifier comprising:
a first transistor having a first source coupled to a first bit line and a first gate configured to receive an input sense signal, wherein the first transistor is configured to supply a first initial voltage to a first output node based on a first voltage of the first bit line when the input sense signal has a first logic level and to isolate the first output node from the first bit line when the input sense signal has a second logic level;
a second transistor having a second source coupled to a second bit line and a second gate connected to the first gate and configured to receive the input sense signal, wherein the second transistor is configured to supply a second initial voltage to a second output node based on a second voltage of the second bit line when the input sense signal has the first logic level and to isolate the second output node from the second bit line when the input sense signal has the second logic level;
a third transistor coupled to the second transistor and having a third gate directly coupled to the second bit line, the third transistor configured to discharge the first output node when the input sense signal has the second logic level;
a fourth transistor coupled to the first transistor and having a fourth gate directly coupled to the first bit line, the fourth transistor configured to discharge the second output node when the input sense signal has the second logic level; and
a fifth transistor having a fifth gate connected to the first gate and configured to receive the input sense signal, the fifth transistor coupled to the third transistor and to the fourth transistor.

2. The apparatus of claim 1 , wherein the first transistor and the second transistor are p-type metal oxide semiconductor (PMOS) transistors.

3. The apparatus of claim 1 , wherein the third transistor and the fourth transistor are n-type metal oxide semiconductor (NMOS) transistors.

4. The apparatus of claim 1 , wherein an initial differential voltage corresponds to a difference between the first initial voltage and the second initial voltage, and wherein, when the input sense signal has the second logic level, the current latched sense amplifier is configured to:
discharge the first output node responsive to a first value of the second bit line;
discharge the second output node responsive to a second value of the first bit line; and
amplify the initial differential voltage responsive to the discharge of the first output node or the discharge of the second output node.

5. The apparatus of claim 1 , wherein the fifth transistor is configured to prevent a first current flow through the third transistor and a second current flow through the fourth transistor when the input sense signal has the first logic level, and wherein the fifth transistor is configured to permit the first current flow through the third transistor and the second current flow through the fourth transistor when the input sense signal has the second logic level.

6. The apparatus of claim 5 , wherein the fifth transistor is configured to be activated based on the input sense signal, and wherein the fifth transistor is configured to provide a first path to ground for the first current flow through the third transistor and to provide a second path to ground for the second current flow through the fourth transistor.

7. The apparatus of claim 1 , wherein the fifth transistor comprises an n-type metal oxide semiconductor (NMOS) transistor, and wherein the fifth transistor is coupled to ground.

8. The apparatus of claim 1 , wherein the current latched sense amplifier further comprises:
a first capacitor coupled to the first output node, wherein the first capacitor is configured to discharge via a first discharge path through the third transistor, and wherein the first discharge path is non-conductive when the input sense signal has the first logic level; and
a second capacitor coupled to the second output node, wherein the second capacitor is configured to discharge via a second discharge path through the fourth transistor, and wherein the second discharge path is non-conductive when the input sense signal has the first logic level.

9. The apparatus of claim 8 , wherein the first capacitor is configured to be charged based on the first voltage of the first bit line when the input sense signal has the first logic level.

10. The apparatus of claim 1 , wherein the first logic level is a low logic level, and wherein the input sense signal has the first logic level during a first phase.

11. The apparatus of claim 1 , wherein the second logic level is a high logic level, and wherein the input sense signal transitions from the first logic level to the second logic level in response to an activation of a second phase.

12. The apparatus of claim 1 , wherein the current latched sense amplifier is integrated into an electronic device comprising a set top box, a music player, a video player, an entertainment unit, a navigation device, a mobile phone, a portable computer, a hand-held personal communication system (PCS) unit, a communications device, a personal digital assistant (PDA), a fixed location data unit, a computer, or a combination thereof.

13. The apparatus of claim 1 , wherein the current latched sense amplifier is integrated into a memory array comprising a plurality of sense amplifiers.

14. The apparatus of claim 1 , wherein the third transistor is configured to be activated based on the second voltage of the second bit line, and wherein the third gate of the third transistor is coupled to the second transistor.

15. The apparatus of claim 1 , further comprising a first inverter and a second inverter, wherein the first inverter and the second inverter are cross-coupled, wherein the first inverter is coupled between a high-voltage bus associated with a supply voltage and the third transistor, and wherein the second inverter is coupled between the high-voltage bus and the fourth transistor.

16. The apparatus of claim 1 , further comprising a sixth transistor and a seventh transistor, wherein the first output node is coupled between the sixth transistor and the seventh transistor.

17. The apparatus of claim 16 , wherein the sixth transistor is coupled to a high voltage bus associated with a supply voltage, and wherein the seventh transistor is coupled between the first output node and the third transistor.

18. The apparatus of claim 16 , wherein the sixth transistor is a p-type metal oxide semiconductor (PMOS) transistor, and wherein the seventh transistor is an n-type metal oxide semiconductor (NMOS) transistor.

19. The apparatus of claim 16 , wherein a sixth gate of the sixth transistor and a seventh gate of the seventh transistor are coupled to the second transistor and to the second output node.

20. An apparatus for sensing a differential between two bit lines, comprising:
means for supplying a first initial voltage to a first output node of a sense amplifier based on a first voltage of a first bit line and for isolating the first bit line from the first output node, wherein the first initial voltage is supplied to the first output node when an input sense signal has a first logic level, and wherein the first bit line is isolated from the first output node when the input sense signal has a second logic level;
means for supplying a second initial voltage to a second output node of the sense amplifier based on a second voltage of a second bit line and for isolating the secon

Assignees

• Chen Nan
• Chaba Ritu
• Qualcomm Inc

Inventors

• Chen Nan
• Chaba Ritu

Classifications

• G11C7/065 Primary

  Differential amplifiers of latching type · CPC title

• G11C7/08

  Control thereof · CPC title

• G11C7/12

  Bit line control circuits, e.g. drivers, boosters, pull-up circuits, pull-down circuits, precharging circuits, equalising circuits, for bit lines · CPC title

• G11C7/00

  Arrangements for writing information into, or reading information out from, a digital store (G11C5/00 takes precedence; auxiliary circuits for stores using semiconductor devices G11C11/4063, G11C11/413) · CPC title