SRAM with burst mode operation

Patent metadata

Field	Value
Publication number	US-11527282-B2
Application number	US-202117144077-A
Country	US
Kind code	B2
Filing date	Jan 7, 2021
Priority date	Jun 4, 2019
Publication date	Dec 13, 2022
Grant date	Dec 13, 2022

Abstract

A memory is provided that is configured to practice both a conventional normal read operation and also a burst mode read operation. During the normal read operation, the memory pre-charges the bit lines in a group of multiplexed columns. Each column has a sense amplifier that latches a bit decision for the column during the normal read operation. If a subsequent read operation addresses the same group of multiplexed columns, the memory invokes the burst-mode read operation during which the bit lines are not pre-charged.

First claim

What is claimed is:

1. A burst-mode method for a static random-access memory (SRAM) comprising:
decoding a first address responsive to a first memory clock cycle, wherein the first address identifies a first column in a group of multiplexed columns;
asserting a word line responsive to the first memory clock cycle;
responsive to the word line assertion: latching in a first sense amplifier a first bit from a first bitcell in the first column while latching in a second sense amplifier a second bit from a second bitcell in a second column in the group of multiplexed columns;
transferring the first bit from the first sense amplifier to latch the first bit in a data output latch responsive to the first memory clock cycle;
decoding a second address responsive to a second memory clock cycle, wherein the second address identifies the second bitcell; and
transferring the second bit from the second sense amplifier to latch the second bit in the data output latch responsive to the second memory clock cycle, wherein the word line is not asserted during the second memory clock cycle.

2. The burst-mode method of claim 1 , wherein sensing the first bit comprises:
while the word line is asserted, initiating a charge-transfer period in which a first charge transfer from a first pre-charged bit line in the first column to a first sense node occurs responsive to the first bit having a first binary value and does not occur responsive to the first bit having a second binary value that is a complement of the first binary value; and
sensing the first bit responsive to the first charge transfer.

3. The burst-mode method of claim 2 , further comprising:
discharging the first sense node prior to the charge-transfer period.

4. The burst-mode method of claim 2 , wherein sensing the first bit comprising latching the first bit in a sense amplifier.

5. The burst-mode method of claim 3 , wherein the first sense node is not discharged during the second memory clock cycle.

6. The burst-mode method of claim 1 , further comprising:
sensing a third bit from a third column in the group of multiplexed columns responsive to the word line assertion;
decoding a third address responsive to a third memory clock cycle, wherein the third address identifies a third bitcell in the third column; and
latching the third bit in the data output latch responsive to the third memory clock cycle, wherein the word line is not asserted during the third memory clock cycle.

Assignees

• Qualcomm Inc

Inventors

• Jung Changho
• Kim Keejong
• Jung Chulmin
• Chaba Ritu

Classifications

• G11C7/103 Primary

  using serially addressed read-write data registers (G11C7/1036 takes precedence) · CPC title

• G11C11/418

  Address circuits · CPC title

• G11C8/08

  Word line control circuits, e.g. drivers, boosters, pull-up circuits, pull-down circuits, precharging circuits, for word lines · CPC title

• G11C7/08

  Control thereof · CPC title

• G11C7/106

  Data output latches · CPC title