SRAM with burst mode operation

Patent metadata

Field	Value
Publication number	US-10923185-B2
Application number	US-201916431639-A
Country	US
Kind code	B2
Filing date	Jun 4, 2019
Priority date	Jun 4, 2019
Publication date	Feb 16, 2021
Grant date	Feb 16, 2021

Abstract

A memory is provided that is configured to practice both a conventional normal read operation and also a burst mode read operation. During the normal read operation, the memory pre-charges the bit lines in a group of multiplexed columns. Each column has a sense amplifier that latches a bit decision for the column during the normal read operation. If a subsequent read operation addresses the same group of multiplexed columns, the memory invokes the burst-mode read operation during which the bit lines are not pre-charged.

First claim

What is claimed is:

1. A memory, comprising:
a first column including a first bitcell coupled to a first pair of bit lines and including a first sense amplifier configured to sense a first bit from the first bitcell through a first pair of sense nodes to output the first bit at a first output terminal for the first column;
a bit line pre-charge circuit configured to pre-charge the first pair of bit lines to a power supply voltage;
a second column including a second sense amplifier configured to sense a second bit from a second bitcell through a second pair of sense nodes and to output the second bit at a second output terminal for the second column;
a data output latch;
a column multiplexer configured to select between the first bit from the first output terminal and the second bit from the second output terminal to provide a selected bit to the data output latch; and
a sense node pre-charge circuit configured to discharge the first pair of sense nodes and the second pair of sense nodes in a normal read operation and to not discharge the first pair of sense nodes and the second pair of sense nodes in a burst-mode read operation.

2. The memory of claim 1 , wherein the first sense amplifier comprises a first latch, and wherein the second sense amplifier comprises a second latch.

3. The memory of claim 1 , wherein the first sense amplifier comprises a pair of cross-coupled NAND gates, and wherein the first output terminal is an output terminal for a first NAND gate in the pair of cross-coupled NAND gates.

4. The memory of claim 1 , wherein the first pair of sense nodes comprises a first sense node and a second sense node, and wherein the sense node pre-charge circuit comprises a first transistor coupled between the first sense node and ground and further comprises a second transistor coupled between the second sense node and ground.

5. The memory of claim 4 , wherein the first pair of bit lines includes a bit line coupled through a first charge-transfer transistor to the first sense node and further includes a complement bit line coupled through a second charge-transfer transistor to the second sense node.

6. The memory of claim 5 , wherein the first charge-transfer transistor and the second charge-transfer transistor are both p-type metal-oxide semiconductor (PMOS) transistors.

7. The memory of claim 5 , wherein an inverter is configured to drive a gate for the first charge-transfer transistor and a gate for the second charge-transfer transistor during a charge-transfer period.

8. The memory of claim 5 , wherein a dummy bit line is configured to drive a gate for the first charge-transfer transistor and a gate for the second charge-transfer transistor during a charge-transfer period.

9. The memory of claim 1 , wherein the first bitcell and the second bitcell each comprises a pair of cross-coupled inverters.

10. The memory of claim 1 , further comprising a word line, wherein the memory is further configured to assert a voltage for the word line during the normal read operation and to maintain the voltage for the word line as discharged during the burst-mode read operation.

11. The memory of claim 1 , wherein the memory is incorporated in a cellular telephone.

12. The memory of claim 1 , wherein the memory is incorporated in a laptop computer.

13. A memory, comprising:
a word line;
a plurality of columns, each column in the plurality of columns including a bit cell at an intersection of the column with the word line, a sense amplifier, and a bit line coupled to a sense node for the sense amplifier through a charge-transfer transistor;
a bit line pre-charge circuit configured to pre-charge the bit line in each column during a normal read operation for the memory;
a column multiplexer for selecting for a bit decision from the sense amplifier in each column to provide an output bit;
a data output latch for latching the output bit;
a sense node pre-charge circuit configured to discharge each sense node in response to an assertion of a sense node pre-charge signal; and
means for asserting the sense node pre-charge signal in a normal read operation and to prevent an assertion of the sense node pre-charge signal in a burst-mode read operation.

14. The memory of claim 13 , wherein the means is further configured to shut off each charge-transfer transistor during the burst-mode read operation.

Assignees

• Qualcomm Inc

Inventors

• Jung Changho
• Kim Keejong
• Jung Chulmin
• Chaba Ritu

Classifications

• G11C7/12

  Bit line control circuits, e.g. drivers, boosters, pull-up circuits, pull-down circuits, precharging circuits, equalising circuits, for bit lines · CPC title

• G11C8/10

  Decoders · CPC title

• G11C8/08

  Word line control circuits, e.g. drivers, boosters, pull-up circuits, pull-down circuits, precharging circuits, for word lines · CPC title

• G11C7/08

  Control thereof · CPC title

• G11C7/103 Primary

  using serially addressed read-write data registers (G11C7/1036 takes precedence) · CPC title