Gate contact structure over active gate and method to fabricate same
US-2026026325-A1 · Jan 22, 2026 · US
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Bohr Mark patents
Bohr Mark is listed as an inventor on 60 patents in our database. Major assignees and classification codes are summarized below.
| Metric | Value |
|---|---|
| Inventor | Bohr Mark |
| Total patents | 60 |
| First publication | Aug 11, 2016 |
| Latest publication | Jan 22, 2026 |
Notable patents
Publications ranked by popularity score, then publication date.
Device layer interconnects
US-12519058-B2 · Jan 6, 2026 · US
Gate contact structure over active gate and method to fabricate same
US-2025233020-A1 · Jul 17, 2025 · US
Gate contact structure over active gate and method to fabricate same
US-12278144-B2 · Apr 15, 2025 · US
Deep trench via for three-dimensional integrated circuit
US-12100705-B2 · Sep 24, 2024 · US
Package on active silicon semiconductor packages
US-11978727-B2 · May 7, 2024 · US
Device layer interconnects
US-2024096791-A1 · Mar 21, 2024 · US
Device layer interconnects
US-11881452-B2 · Jan 23, 2024 · US
Device, system and method for providing inductor structures
US-11830829-B2 · Nov 28, 2023 · US
Device, method and system for providing a stacked arrangement of integrated circuit dies
US-11749663-B2 · Sep 5, 2023 · US
Recent patents
Latest publications not already listed above.
Die interconnection scheme for providing a high yielding process for high performance microprocessors
US-2023245974-A1 · Aug 3, 2023 · US
Substrate-less FinFET diode architectures with backside metal contact and subfin regions
US-11652107-B2 · May 16, 2023 · US
Die interconnection scheme for providing a high yielding process for high performance microprocessors
US-11652060-B2 · May 16, 2023 · US
Self-aligned gate edge and local interconnect
US-11563081-B2 · Jan 24, 2023 · US
Device layer interconnects
US-2022319978-A1 · Oct 6, 2022 · US
Integrated circuit structures having asymmetric source and drain structures
US-11462536-B2 · Oct 4, 2022 · US
Device, system and method for providing inductor structures
US-2022302051-A1 · Sep 22, 2022 · US
Deep trench via for three-dimensional integrated circuit
US-2022285342-A1 · Sep 8, 2022 · US
Device, method and system for providing a stacked arrangement of integrated circuit dies
US-2022271022-A1 · Aug 25, 2022 · US
Device layer interconnects
US-11410928-B2 · Aug 9, 2022 · US
Device, system and method for providing inductor structures
US-11387198-B2 · Jul 12, 2022 · US
Device, method and system for providing a stacked arrangement of integrated circuit dies
US-11373987-B2 · Jun 28, 2022 · US
Deep trench via for three-dimensional integrated circuit
US-11373999-B2 · Jun 28, 2022 · US
Copper-filled trench contact for transistor performance improvement
US-2022115505-A1 · Apr 14, 2022 · US
Designs and methods for conductive bumps
US-2022059484-A1 · Feb 24, 2022 · US
High density and fine pitch interconnect structures in an electric test apparatus
US-11249113-B2 · Feb 15, 2022 · US
Designs and methods for conductive bumps
US-11201129-B2 · Dec 14, 2021 · US
Gate contact structure over active gate and method to fabricate same
US-2021210385-A1 · Jul 8, 2021 · US
Gate contact structure over active gate and method to fabricate same
US-11004739-B2 · May 11, 2021 · US
High density and fine pitch interconnect structures in an electric test apparatus
US-2021088554-A1 · Mar 25, 2021 · US
Major assignees
Companies most often associated with this inventor's publications.
| Assignee | Patents |
|---|---|
| Intel Corp | 59 |
| Bohr Mark | 3 |
| Pethe Abhijit Jayant | 2 |
| Ghani Tahir | 2 |
| Webb Clair | 2 |
Top CPC classifications
Most common classification codes across this inventor's patents.
| CPC | Patents |
|---|---|
| H10W20/20 | 26 |
| H10D30/62 | 26 |
| H10D64/017 | 23 |
| H10W20/42 | 22 |
| H01L29/66545 | 21 |