Device, system and method for providing inductor structures

Patent metadata

Field	Value
Publication number	US-11830829-B2
Application number	US-202217836117-A
Country	US
Kind code	B2
Filing date	Jun 9, 2022
Priority date	Sep 29, 2017
Publication date	Nov 28, 2023
Grant date	Nov 28, 2023

Abstract

Techniques and mechanisms for providing an inductor with an integrated circuit (IC) die. In an embodiment, the IC die comprises integrated circuitry and one or more first metallization layers. The IC die is configured to couple to a circuit device including one or more second metallization layers, where such coupling results in the formation of an inductor which is coupled to the integrated circuitry. One or more loop structures of the inductor each span both some or all of the one or more first metallization layers and some or all of the one or more second metallization layers. In another embodiment, the IC die or the circuit device includes a ferromagnetic material to concentrate a magnetic flux which is provided with the inductor.

First claim

What is claimed is:

1. A method comprising:
providing a first integrated circuit (IC) die including first integrated circuitry and one or more first metallization layers;
coupling the first IC die to a second circuit device via first contacts in or on a side of the IC die, wherein the coupling forms an inductor coupled to the first integrated circuitry, wherein one or more loop structures of the inductor each include:
a respective first conductor portion of the one or more first metallization layers; and
a respective second conductor portion of one or more second metallization layers of the second circuit device, the respective second conductor portion coupled to the first conductor portion.

2. The method of claim 1 , further comprising disposing a mold compound over the first IC die or the second circuit device.

3. The method of claim 1 , further comprising:
sending an input signal from the first integrated circuitry to the inductor; and
receiving at the first integrated circuitry an output from the inductor, the output signal based on the input signal.

4. The method of claim 1 , wherein the second circuit device is a second IC die comprising a semiconductor substrate and a device layer.

5. The method of claim 1 , wherein the inductor includes multiple loop structures each spanning a respective portion of the one or more first metallization layers and a respective portion of the one or more second metallization layers.

6. The method of claim 1 , wherein the first IC die or the second circuit device further comprises a ferromagnetic structure configured to shape a magnetic field generated with the inductor.

7. The method of claim 6 , wherein the ferromagnetic structure includes a ferromagnetic ring.

8. A method of fabricating a system, the method comprising:
providing a first integrated circuit (IC) die including:
a semiconductor substrate and first integrated circuitry; and
one or more first metallization layers coupled between the first integrated circuitry and a hardware interface;

coupling a second circuit device to the first IC die, the second circuit device including one or more second metallization layers coupled to the one or more first metallization layers via the hardware interface;
coupling an inductor to the first integrated circuitry, wherein one or more loop structures of the inductor each include:
a respective first conductor portion of the one or more first metallization layers; and
a respective second conductor portion of one or more second metallization layers of the second circuit device, the respective second conductor portion coupled to the first conductor portion.

9. The method of claim 8 , wherein the second circuit device is a second IC die comprising a semiconductor substrate and a device layer.

10. The method of claim 8 , wherein the second circuit device is a package substrate.

11. The method of claim 8 , wherein the second circuit device is an interposer.

12. The method of claim 8 , wherein the inductor includes multiple loop structures each spanning a respective portion of the one or more first metallization layers and a respective portion of the one or more second metallization layers.

13. The method of claim 8 , wherein the first IC die or the second circuit device further comprises a ferromagnetic structure configured to shape a magnetic field generated with the inductor.

14. The method of claim 13 , wherein the ferromagnetic structure includes a ferromagnetic ring.

15. The method of claim 8 , wherein the first integrated circuitry includes a bridge circuit.

16. The method of claim 8 , wherein the first integrated circuitry includes a voltage regulator circuit.

Assignees

• Intel Corp

Inventors

• Gomes Wilfred
• Bohr Mark
• Ingerly Doug
• Kumar Rajesh
• Krishnamurthy Harish
• Desai Nachiket Venkappayya

Classifications

• H10W90/752

  between stacked chips · CPC title

• H10W90/724

  between a chip and a stacked insulating package substrate, interposer or RDL · CPC title

• H10W90/722

  between stacked chips · CPC title

• H10W90/293

  characterised by non-galvanic coupling between the chips, e.g. capacitive coupling · CPC title

• H10W90/291

  characterised by containers, encapsulations, or other housings for the stacked chips · CPC title