Deep trench via for three-dimensional integrated circuit

Patent metadata

Field	Value
Publication number	US-12100705-B2
Application number	US-202217825664-A
Country	US
Kind code	B2
Filing date	May 26, 2022
Priority date	Jun 7, 2018
Publication date	Sep 24, 2024
Grant date	Sep 24, 2024

Abstract

Described herein are apparatuses, methods, and systems associated with a deep trench via in a three-dimensional (3D) integrated circuit (IC). The 3D IC may include a logic layer having an array of logic transistors. The 3D IC may further include one or more front-side interconnects on a front side of the 3D IC and one or more back-side interconnects on a back side of the 3D IC. The deep trench may be in the logic layer to conductively couple a front-side interconnect to a back-side interconnect. The deep trench via may be formed in a diffusion region or gate region of a dummy transistor in the logic layer. Other embodiments may be described and claimed.

First claim

What is claimed is:

1. A three-dimensional (3D) integrated circuit (IC) assembly comprising:
a first IC die that includes:
a logic layer including a transistor array with a plurality of logic transistors, wherein the plurality of logic transistors includes a plurality of fins of semiconductor material;
a first interconnect on a first side of the logic layer;
a second interconnect on a second side of the logic layer, wherein the second side is opposite the first side; and
a deep trench via in the logic layer to conductively couple the first interconnect with the second interconnect, wherein the second side is opposite the first side, and wherein the deep trench via extends through a diffusion region or a gate region of a dummy transistor of the transistor array; and

a second IC die coupled to a front side of the first IC die, wherein the second IC die is to communicate with another device via the first interconnect, the deep trench via, and the second interconnect.

2. The 3D IC assembly of claim 1 , wherein the dummy transistor is between individual logic transistors of the plurality of logic transistors.

3. The 3D IC assembly of claim 1 , wherein one or more fins of the plurality of fins are in the diffusion region, and wherein the deep trench via is around the one or more fins.

4. The 3D IC assembly of claim 1 , wherein the fins do not extend into the deep trench via.

5. The 3D IC assembly of claim 1 , wherein the deep trench via includes a first portion on a second portion, wherein the first portion has a greater width than a second portion in a direction that is transverse to a long axis of the plurality of fins.

6. The 3D IC assembly of claim 1 , further comprising a via to electrically couple the deep trench via to the first interconnect, wherein the via has a width that is less than a width of the deep trench via.

7. The 3D IC assembly of claim 1 , wherein the deep trench via extends across multiple fins of the plurality of fins.

8. The 3D IC assembly of claim 1 , further comprising a sidewall spacer between the deep trench via and an adjacent gate region or diffusion region.

9. The 3D IC assembly of claim 8 , wherein the conductive material is in the diffusion region of the dummy transistor, and wherein the sidewall spacer is between the diffusion region and the adjacent gate region.

10. The 3D IC assembly of claim 9 , wherein the adjacent gate region includes a gate stack of a logic transistor.

11. The 3D IC assembly of claim 8 , wherein the conductive material is in the gate region of the dummy transistor, and wherein the sidewall spacer is between the gate region and the adjacent diffusion region.

12. The 3D IC assembly of claim 1 , wherein a backside of the first die is coupled to a motherboard, and wherein the another device is coupled to the motherboard.

13. An integrated circuit (IC) die comprising:
a logic layer including a transistor array with a plurality of fins of semiconductor material;
a deep trench via in the logic layer to electrically couple a first interconnect on a first side of the logic layer with a second interconnect on a second side of the logic layer, wherein the second side is opposite the first side, and wherein the deep trench via includes a conductive material in a diffusion region or a gate region of a dummy transistor of the transistor array; and
a sidewall spacer between the conductive material in the diffusion region or the gate region of the dummy transistor and an adjacent gate region or diffusion region.

14. The IC die of claim 13 , wherein the dummy transistor is between individual logic transistors in the logic layer.

15. The IC die of claim 13 , wherein one or more fins of the plurality of fins are in the diffusion region, and wherein the deep trench via is around the one or more fins.

16. The IC die of claim 13 , wherein the fins do not extend into the deep trench via.

17. The IC die of claim 13 , wherein the deep trench via includes a first portion on a second portion, wherein the first portion has a greater width than a second portion in a direction that is transverse to a long axis of the plurality of fins.

18. The IC die of claim 13 , further comprising a via to electrically couple the deep trench via to the first interconnect, wherein the via has a width that is less than a width of the deep trench via.

19. The IC die of claim 13 , wherein the conductive material is in the diffusion region of the dummy transistor, and wherein the sidewall spacer is between the diffusion region and the adjacent gate region.

20. The IC die of claim 13 , wherein the conductive material is in the gate region of the dummy transistor, and wherein the sidewall spacer is between the gate region and the adjacent diffusion region.

21. A computer system comprising:
a circuit board;
a first integrated circuit (IC) die having a first side and a second side, wherein the first side is coupled to the circuit board, and wherein the first IC die includes:
a logic layer including a transistor array with a plurality of fins of semiconductor material to form a plurality of logic transistors;
a first interconnect toward the first side from the logic layer;
a second interconnect toward the second side from the logic layer; and
a deep trench via in the logic layer to electrically couple the first interconnect with the second interconnect, wherein the deep trench via is in a diffusion region or a gate region of a dummy transistor in the transistor array;

a second IC die coupled to the second side of the IC die, wherein the second IC die is conductively coupled to another device on the circuit board via the second interconnect, the deep trench via, and the first interconnect.

22. The computer system of claim 21 , wherein the first IC die further includes a sidewall spacer between the diffusion region and an adjacent gate region or between the gate region and an adjacent diffusion region.

23. The computer system of claim 21 , wherein the dummy transistor is between individual logic transistors of the plurality of logic transistors.

24. The computer system of claim 21 , wherein one or more fins of the plurality of fins are in the diffusion region or gate region, and wherein the deep trench via is around the one or more fins.

25. The computer system of claim 21 , further comprising one or more of an antenna, a display, a network adapter, or a memory device coupled to the IC die.

Assignees

• Intel Corp

Inventors

• Wang Yih
• Mehandru Rishabh
• Kobrinsky Mauro J
• Ghani Tahir
• Bohr Mark
• Nabors Marni

Classifications

• H10W20/481

  on the rear surfaces of the wafers or substrates · CPC title

• H10W20/2134

  TSVs extending from the semiconductor wafer into back-end-of-line layers · CPC title

• H10W20/056

  by filling conductive material into holes, grooves or trenches · CPC title

• H10W20/42

  Vias, e.g. via plugs · CPC title

• H10W20/023

  the interconnections being through-semiconductor vias · CPC title