Designs and methods for conductive bumps

Patent metadata

Field	Value
Publication number	US-11201129-B2
Application number	US-201916283582-A
Country	US
Kind code	B2
Filing date	Feb 22, 2019
Priority date	Sep 22, 2003
Publication date	Dec 14, 2021
Grant date	Dec 14, 2021

Abstract

Methods, techniques, and structures relating to die packaging. In one exemplary implementation, a die package interconnect structure includes a semiconductor substrate and a first conducting layer in contact with the semiconductor substrate. The first conducting layer may include a base layer metal. The base layer metal may include Cu. The exemplary implementation may also include a diffusion barrier in contact with the first conducting layer and a wetting layer on top of the diffusion barrier. A bump layer may reside on top of the wetting layer, in which the bump layer may include Sn, and Sn may be electroplated. The diffusion barrier may be electroless and may be adapted to prevent Cu and Sn from diffusing through the diffusion barrier. Furthermore, the diffusion barrier may be further adapted to suppress a whisker-type formation in the bump layer.

First claim

What is claimed is:

1. An assembly comprising:
a die;
a pad disposed on the die, the pad including aluminum;
a base layer metal on the pad, the base layer metal including an adhesion layer directly on the pad, a layer of aluminum directly on the adhesion layer, and a seed layer directly on the layer of aluminum, wherein the adhesion layer comprises titanium, and wherein the seed layer comprises nickel or cobalt;
a diffusion barrier layer directly on the base layer metal, the diffusion barrier layer including nickel, wherein the diffusion barrier layer has a non-planar top surface;
a copper bump above and directly on and in direct contact with the non-planar top surface of the diffusion barrier layer, wherein an entirety of the copper bump has a planar top surface; and
a solder layer above and directly on the planar top surface of the copper bump, the solder layer comprising tin, silver and copper.

2. The assembly of claim 1 , further comprising a package, the package comprising a package layer coupled to the solder layer.

3. The assembly of claim 1 , wherein the die is a silicon die.

4. The assembly of claim 1 , wherein the diffusion barrier further includes phosphorous.

5. The assembly of claim 1 , wherein the diffusion barrier further includes boron.

6. The assembly of claim 1 , wherein the solder layer further includes bismuth.

7. The assembly of claim 1 , wherein the solder layer further includes antimony.

8. The assembly of claim 1 , wherein the assembly is substantially free of lead.

Assignees

• Intel Corp

Inventors

• Dubin Valery M
• Balakrishnan Sridhar
• Bohr Mark

Classifications

• H10W95/00

  Packaging processes not covered by the other groups of this subclass · CPC title

• H10W72/352

  comprising metals or metalloids, e.g. solders · CPC title

• H10W72/251

  Materials · CPC title

• H10W72/252

  comprising solid metals or solid metalloids, e.g. PbSn, Ag or Cu · CPC title

• H10W72/01235

  by plating, e.g. electroless plating or electroplating · CPC title