Substrate-less FinFET diode architectures with backside metal contact and subfin regions

Patent metadata

Field	Value
Publication number	US-11652107-B2
Application number	US-201916447874-A
Country	US
Kind code	B2
Filing date	Jun 20, 2019
Priority date	Jun 20, 2019
Publication date	May 16, 2023
Grant date	May 16, 2023

Abstract

Embodiments include diode devices and transistor devices. A diode device includes a first fin region over a first conductive region and an insulator region, and a second fin region over a second conductive and insulator regions, where the second fin region is laterally adjacent to the first fin region, and the insulator region is between the first and second conductive regions. The diode device includes a first conductive via on the first conductive region, where the first conductive via is vertically adjacent to the first fin region, and a second conductive via on the second conductive region, where the second conductive via is vertically adjacent to the second fin region. The diode device may include conductive contacts, first portions on the first fin region, second portions on the second fin region, and gate electrodes between the first and second portions and the conductive contacts.

First claim

What is claimed is:

1. A diode device, comprising:
a first fin region over a first conductive region and an insulator region;
a second fin region over a second conductive region and the insulator region, wherein the second fin region is laterally adjacent to the first fin region, and wherein the insulator region is between the first conductive region and the second conductive region;
a first conductive via on the first conductive region, wherein the first conductive via is vertically adjacent to the first fin region; and
a second conductive via on the second conductive region, wherein the second conductive via is vertically adjacent to the second fin region.

2. The diode device of claim 1 , further comprising:
a plurality of first portions on the first fin region;
a plurality of second portions on the second fin region;
a plurality of gate electrodes over the first and second fin regions, wherein the plurality of gate electrodes are between the plurality of first and second portions; and
a plurality of conductive contacts over the plurality of first and second portions and the first and second fin regions, wherein the plurality of gate electrodes are between the plurality of conductive contacts.

3. The diode device of claim 2 , wherein the first and second conductive vias are coupled to the plurality of conductive contacts.

4. The diode device of claim 1 , wherein the first fin region includes a first N-type doped material, and wherein the second fin region includes a first P-type doped material.

5. The diode device of claim 2 , wherein the plurality of first portions includes a second N-type doped material, and wherein the plurality of second portions includes a second P-type doped material.

6. The diode device of claim 2 , wherein the plurality of gate electrodes includes a polysilicon material.

7. The diode device of claim 2 , further comprising a plurality of conductive lines over the plurality of conductive contacts.

8. The diode device of claim 1 , wherein the first conductive region is a cathode region, wherein the second conductive region is an anode region, and wherein the first fin region has an interface sidewall that is directly adjacent and coupled to an interface sidewall of the second fin region.

9. The diode device of claim 2 , wherein the first and second conductive vias have a top surface that is substantially coplanar to a top surface of the plurality of conductive contacts.

10. The diode device of claim 8 , wherein the first conductive via is conductively coupled to the cathode region, wherein the second conductive via is conductive coupled to the anode region, and wherein the interface sidewalls of the first and second fin regions are positioned over the insulator region.

Assignees

• Intel Corp

Inventors

• THOMSON Nicholas
• Kar Ayan
• Kolluru Kalyan
• Jack Nathan
• Ma Rui
• Bohr Mark
• Mehandru Rishabh
• Rao Halady Arpit

Classifications

• H10D89/611

  using diodes as protective elements · CPC title

• H10D86/215

  comprising FinFETs · CPC title

• H10D86/01

  Manufacture or treatment · CPC title

• H10D8/422

  PN diodes having the PN junctions in mesas · CPC title

• H10D30/62

  Fin field-effect transistors [FinFET] · CPC title