High density and fine pitch interconnect structures in an electric test apparatus

Patent metadata

Field	Value
Publication number	US-11249113-B2
Application number	US-202017111298-A
Country	US
Kind code	B2
Filing date	Dec 3, 2020
Priority date	Jan 5, 2018
Publication date	Feb 15, 2022
Grant date	Feb 15, 2022

Abstract

An electrical-test apparatus is provided, which includes a MEMS array. In an example, the MEMS array comprises a plurality of tester interconnect structures cantilevered from first terminals on a first side of a substrate. The tester interconnect structures may have a first diameter. In an example, the MEMS array comprises a plurality of through-substrate vias that extend through the substrate, the vias having a second diameter larger than the first diameter. In an example, individual ones of the vias electrically couple individual ones of the tester interconnect structures to corresponding ones of second terminals on a second side of the substrate.

First claim

We claim:

1. An electrical-test probe array, comprising:
a plurality of through-substrate vias (TSVs) that extend through a substrate, the TSVs comprising electrically conductive material;
a plurality of probes comprising electrically conductive material cantilevered from a surface on a first side of the substrate, individual ones of the probes electrically coupled to individual ones of the TSVs; and
a plurality of terminals over a second side of the substrate, wherein individual ones of the terminals are electrically coupled to individual ones of the TSVs.

2. The electrical-test probe array of claim 1 , wherein a base of individual ones of the probes is in direct contact with individual ones of the TSVs, and a pitch of the probes is substantially equal to a pitch of the TSVs.

3. The electrical-test probe array of claim 2 , wherein a base of individual ones of the probes is in direct contact with individual ones of a plurality of second terminals over the first side of the substrate, the second terminals electrically coupled to the TSVs through one or more interconnect levels that are over the first side of the substrate.

4. The electrical-test probe array of claim 1 , wherein the TSVs have a first pitch, greater than a second pitch of the probes.

5. The electrical-test probe array of claim 4 , wherein the probes have a pitch of 15 μm, or less.

6. The electrical-test probe array of claim 1 , wherein the substrate comprises a crystal comprising silicon.

7. The electrical-test probe array of claim 1 , wherein the probes protrude at least 100 μm from the surface.

8. The electrical-test probe array of claim 1 , wherein the probes extend in substantially the same direction relative to a plane of the substrate.

9. The electrical-test probe array of claim 8 , wherein the probes extend in a direction substantially normal to the plane of the substrate.

10. The electrical-test probe array of claim 8 , wherein the probes extend in a direction non-normal to the plane of the substrate.

11. The electrical-test probe array of claim 1 , wherein the probes have a diameter no more than 30 μm.

12. The electrical-test probe array of claim 1 , wherein individual ones of the probes have a bend between the free end and the base.

13. An electrical-test system comprising:
an electrical-test probe array, comprising:
a plurality of through-substrate vias (TSVs) that extend through a substrate, the TSVs comprising electrically conductive material;
a plurality of probes comprising electrically conductive material cantilevered from a surface on a first side of the substrate, individual ones of the probes having a base electrically coupled to individual ones of the TSVs; and
a plurality of first terminals over a second side of the substrate, wherein individual ones of the first terminals are electrically coupled to individual ones of the TSVs; and

a space transformer electrically coupled to the first terminals, wherein the space transformer comprises a plurality of traces electrically coupling the first terminals to second terminals on a side of the space transformer opposite the first terminals, and wherein the second terminals have a pitch greater than a pitch of the first terminals.

14. The electrical-test system of claim 13 , further comprising:
a memory to store instructions to test Integrated Circuit (IC) devices; and
a processor to execute the instructions to electrically test an IC device through contact between interconnect structures on the IC device and corresponding ones of the probes.

15. A method, comprising:
etching recesses into a substrate from a first side of the substrate;
forming conductive vias by filling the recesses with a conductive material;
forming a plurality of through-substrate vias (TSVs) by thinning the substrate from a second side until the conductive vias are exposed; and
forming a plurality of conductive probes electrically coupled to the vias by plating a conductive material up from the first or second side of the substrate.

16. The method of claim 15 , wherein plating the conductive material further comprises:
forming a mask material over the first or second side of the substrate;
forming a plurality of openings within the mask material;
depositing the conductive material within the openings; and
removing the mask material.

17. The method of claim 16 , wherein individual ones of the openings are over corresponding ones of the TSVs.

18. The method of claim 16 , wherein forming a plurality of openings comprises exposing a photoresist with a source of light tilted at a non-normal angle with respect to a plane of the substrate.

19. The method of 15 , further comprising forming one or more levels of interconnects over the first or a second side of the substrate, and electrically coupled to the TSVs.

20. The method of claim 18 , wherein plating the conductive material up from the first or second side of the substrate comprises plating the conductive material up from terminals of the one or more levels of interconnects.

Assignees

• Intel Corp

Inventors

• Tadayon Pooya
• Bohr Mark
• Walczyk Joe

Classifications

• H10W20/0245

  comprising use of blind vias during the manufacture · CPC title

• H10P76/204

  of organic photoresist masks · CPC title

• H10W78/00

  Detachable holders for supporting packaged chips in operation · CPC title

• H10W70/698

  Semiconductor materials that are electrically insulating, e.g. undoped silicon · CPC title

• H10W70/095

  of vias therein · CPC title