Package on active silicon semiconductor packages

Patent metadata

Field	Value
Publication number	US-11978727-B2
Application number	US-201716641922-A
Country	US
Kind code	B2
Filing date	Sep 28, 2017
Priority date	Sep 28, 2017
Publication date	May 7, 2024
Grant date	May 7, 2024

Abstract

Systems and methods for providing a low profile stacked die semiconductor package in which a first semiconductor package is stacked with a second semiconductor package and both semiconductor packages are conductively coupled to an active silicon substrate that communicably couples the first semiconductor package to the second semiconductor package. The first semiconductor package may conductively couple to the active silicon substrate using a plurality of interconnects disposed in a first interconnect pattern having a first interconnect pitch. The second semiconductor package may conductively couple to the active silicon substrate using a plurality of interconnects disposed in a second interconnect pattern having a second pitch that is greater than the first pitch. The second semiconductor package may be stacked on the first semiconductor package and conductively coupled to the active silicon substrate using a plurality of conductive members or a plurality of wirebonds.

First claim

What is claimed is:

1. A package-on-silicon (PoS) semiconductor package, comprising:
an active silicon substrate, the active silicon substrate including semiconductor devices, and the active silicon substrate having:
an upper surface;
a lower surface; and
a plurality of conductive structures disposed across the upper surface;
wherein the plurality of conductive structures includes:
a first portion of conductive structures disposed in a first pattern across the upper surface of the active silicon substrate, the first portion of conductive structures having a first density; and
a second portion of conductive structures disposed in a second pattern across the upper surface of the active silicon substrate, the second portion of conductive structures having a second density, wherein the first density is greater than the second density;

a first semiconductor package having an upper surface, a lower surface, and a plurality of conductive bumps disposed in the first pattern across the lower surface of the first semiconductor package, the first semiconductor package above the active silicon substrate and comprising a semiconductor die, the semiconductor die having a height above the active silicon substrate;
wherein the plurality of conductive bumps communicably couple the first semiconductor package to the first portion of conductive structures disposed on the active silicon substrate;

a thermally conductive adhesive layer over and in contact with the upper surface of the first semiconductor package, the thermally conductive adhesive layer in direct contact with and extending laterally beyond the semiconductor die of the first semiconductor package; and
a second semiconductor package having an upper surface and a lower surface;
the second semiconductor package disposed such that at least a portion of the first semiconductor package is disposed between the lower surface of the second semiconductor package and the upper surface of the active silicon substrate; and
the second semiconductor package communicably coupled, via a plurality of conductive members, to at least some of the second portion of conductive structures disposed on the active silicon substrate, wherein the active silicon substrate communicably couples the first semiconductor package to the second semiconductor package, wherein the height of the semiconductor die above the active silicon substrate is at least as high as a height of the plurality of conductive members above the active silicon substrate;

wherein the first pattern comprises conductive structures disposed on a first pitch of 50 micrometers (μm) or less; and
wherein the second pattern comprises conductive structures disposed on a second pitch of 150 μm or more; and
an interposer layer disposed between the upper surface of the first semiconductor package and the lower surface of the second semiconductor package, the interposer layer including:
a plurality of conductive pads disposed across an upper surface of the interposer layer;
a plurality of conductive structures disposed across at least a portion of a lower surface of the interposer layer; and
a plurality of conductors communicably coupling at least some of the plurality of conductive pads disposed on the upper surface of the interposer layer to at least some of the plurality of conductive structures disposed on the lower surface of the interposer layer.

2. The PoS semiconductor package of claim 1 wherein one or more adhesives physically couple the lower surface of the second semiconductor package to at least a portion of the upper surface of the first semiconductor package.

3. The PoS semiconductor package of claim 2 wherein the lower surface of the second semiconductor package overhangs at least a portion of an edge of the upper surface of the first semiconductor package.

4. The PoS semiconductor package of claim 3 ;
wherein the plurality of conductive members are on the lower surface of the second semiconductor package and include a plurality of conductive bumps disposed about the portion of the second semiconductor package that overhangs the upper surface of the first semiconductor package; and
wherein the plurality of conductive members comprise a plurality of conductive pillars that communicably couple at least some of the plurality of conductive bumps disposed about the portion of the second semiconductor package that overhangs the upper surface of the first semiconductor package to at least some of the second portion of conductive structures disposed on the upper surface of the active silicon substrate.

5. The PoS semiconductor package of claim 1 :
wherein each of at least some of the plurality of conductive structures disposed on the lower surface of the second semiconductor package physically and communicably couple to corresponding ones of the plurality of conductive pads disposed across the upper surface of the interposer layer; and
wherein the interposer layer includes an adhesive disposed across at least a portion of the lower surface of the interposer layer to physically couple the second semiconductor package and the interposer layer to the first semiconductor package.

6. The PoS semiconductor package of claim 5 wherein the lower surface of the interposer layer overhangs at least a portion of an edge of the upper surface of the first semiconductor package.

7. The PoS semiconductor package of claim 6 ;
wherein the plurality of conductive structures on the lower surface of the interposer layer include a plurality of conductive bumps disposed about the portion of the interposer layer that overhangs the upper surface of the first semiconductor package; and
wherein the plurality of conductive members comprise a plurality of conductive pillars that communicably couple each of at least some of the conductive bumps disposed about the portion of the interposer layer that overhangs the upper surface of the first semiconductor package to corresponding ones of the second portion of conductive structures disposed on the upper surface of the active silicon substrate.

8. The PoS semiconductor package of claim 1 :
wherein the plurality of conductive members communicably coupled to the second semiconductor package comprise a plurality of wirebonds communicably coupled to the second semiconductor package; and
wherein each of at least some of the plurality of wirebonds communicably couple to corresponding ones of the second portion of conductive structures disposed on the surface of the active silicon substrate.

9. A package-on-silicon (PoS) semiconductor package
manufacturing method, comprising:
conductively coupling each of a plurality of conductive structures disposed on a lower surface of a first semiconductor package to corresponding ones of a first portion of conductive structures disposed in a first pattern across an upper surface of an active silicon substrate, the first semiconductor package comprising a semiconductor die, the semiconductor die having a height above the active silicon substrate, the first portion of conductive structures having a first density, and the active silicon substrate including semiconductor devices;
forming a thermally conductive adhesive layer over and in contact with an upper surface of the first semiconductor package, the thermally conductive adhesive layer in direct contact with and extending laterally beyond the semiconductor die of the first semiconductor package;
conductively coupling each of a plurality of conductive structures disposed on a second semiconductor package to corresponding ones of a second portion of conductive structures disposed in a second pattern across the upper surface of the active silicon substrate via a plurality of conductive members, the second portion of conduct

Assignees

• Intel Corp

Inventors

• Gomes Wilfred
• Ganesan Sanka
• Ingerly Doug
• Sankman Robert
• Bohr Mark
• Mallik Debendra

Classifications

• H10W99/00

  Subject matter not provided for in other groups of this subclass · CPC title

• H10W90/752

  between stacked chips · CPC title

• H10W90/722

  between stacked chips · CPC title

• H10W90/291

  characterised by containers, encapsulations, or other housings for the stacked chips · CPC title

• H10W90/20

  Configurations of stacked chips · CPC title