Infrastructure processing unit
US-12405843-B2 · Sep 2, 2025 · US
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Bernstein Debra patents
Bernstein Debra is listed as an inventor on 26 patents in our database. Major assignees and classification codes are summarized below.
| Metric | Value |
|---|---|
| Inventor | Bernstein Debra |
| Total patents | 26 |
| First publication | Mar 19, 2015 |
| Latest publication | Sep 2, 2025 |
Notable patents
Publications ranked by popularity score, then publication date.
Memory thin provisioning using memory pools
US-12373335-B2 · Jul 29, 2025 · US
Accelerator fabric for discrete graphics
US-2022113967-A1 · Apr 14, 2022 · US
Techniques for processor queue management
US-11134021-B2 · Sep 28, 2021 · US
Memory thin provisioning using memory pools
US-2021200667-A1 · Jul 1, 2021 · US
Infrastructure processing unit
US-2021117242-A1 · Apr 22, 2021 · US
Infrastructure processing unit
US-2021117249-A1 · Apr 22, 2021 · US
Multi-core communication acceleration using hardware queue device
US-10929323-B2 · Feb 23, 2021 · US
Bit check processors, methods, systems, and instructions to check a bit with an indicated check bit value
US-10761979-B2 · Sep 1, 2020 · US
Multi-core communication acceleration using hardware queue device
US-2020042479-A1 · Feb 6, 2020 · US
Recent patents
Latest publications not already listed above.
Multi-core communication acceleration using hardware queue device
US-10445271-B2 · Oct 15, 2019 · US
Technologies for a distributed hardware queue manager
US-10216668-B2 · Feb 26, 2019 · US
Technologies for moving workloads between hardware queue managers
US-2019042305-A1 · Feb 7, 2019 · US
Techniques for processor queue management
US-2018191630-A1 · Jul 5, 2018 · US
Bit check processors, methods, systems, and instructions to check a bit with an indicated check bit value
US-2018004655-A1 · Jan 4, 2018 · US
Memory mapping in a processor having multiple programmable units
US-9830284-B2 · Nov 28, 2017 · US
Memory mapping in a processor having multiple programmable units
US-9830285-B2 · Nov 28, 2017 · US
Memory mapping in a processor having multiple programmable units
US-9824037-B2 · Nov 21, 2017 · US
Memory mapping in a processor having multiple programmable units
US-9824038-B2 · Nov 21, 2017 · US
Arbitrating memory accesses via a shared memory fabric
US-9535860-B2 · Jan 3, 2017 · US
Memory mapping in a processor having multiple programmable units
US-2016070664-A1 · Mar 10, 2016 · US
Memory mapping in a processor having multiple programmable units
US-2016071558-A1 · Mar 10, 2016 · US
Memory mapping in a processor having multiple programmable units
US-2016034420-A1 · Feb 4, 2016 · US
Memory mapping in a processor having multiple programmable units
US-2016019178-A1 · Jan 21, 2016 · US
Memory mapping in a processor having multiple programmable units
US-9128818-B2 · Sep 8, 2015 · US
Memory mapping in a processor having multiple programmable units
US-2015081999-A1 · Mar 19, 2015 · US
Major assignees
Companies most often associated with this inventor's publications.
| Assignee | Patents |
|---|---|
| Intel Corp | 26 |
Top CPC classifications
Most common classification codes across this inventor's patents.
| CPC | Patents |
|---|---|
| G11C7/1072 | 12 |
| G06F12/0284 | 12 |
| G06F12/109 | 10 |
| G06F12/06 | 10 |
| G06F12/0806 | 10 |