Memory mapping in a processor having multiple programmable units

Patent metadata

Field	Value
Publication number	US-9824037-B2
Application number	US-201514882824-A
Country	US
Kind code	B2
Filing date	Oct 14, 2015
Priority date	Dec 27, 1999
Publication date	Nov 21, 2017
Grant date	Nov 21, 2017

Abstract

The disclosure includes, in general, among other aspects, an apparatus having multiple programmable units integrated within a processor. The apparatus has circuitry to map addresses in a single address space to resources within the multiple programmable units where the single address space includes addresses for different ones of the resources in different ones of the multiple programmable units and where there is a one-to-one correspondence between respective addresses in the single address space and resources within the multiple programmable units.

First claim

What is claimed is:

1. A processor comprising:
a synchronous dynamic random access memory (SDRAM) controller to couple to an SDRAM;
a plurality of programmable multithreaded processing engines to process network packets, the plurality of programmable multithreaded processing engines having memory mapped registers;
a reduced instruction set computer (RISC) processor coupled to the SDRAM controller and the plurality of programmable multithreaded processing engines, the RISC processor to receive and process packets from the plurality of programmable multithreaded processing engines;
and circuitry to enable the RISC processor to transfer data to and from the memory mapped registers of the plurality of programmable multithreaded processing engines, the circuitry comprising translation logic coupled to the RISC processor and the plurality of programmable multithreaded processing engines, the translation logic to convert a read or write operation in a first format to a corresponding read or write operation in a second format to enable the RISC processor to transfer data to and from the memory mapped registers of the plurality of programmable multithreaded processing engines.

2. The processor of claim 1 , further comprising an interface unit to couple a gigabit Ethernet device to the plurality of programmable multithreaded processing engines.

Assignees

• Intel Corp

Inventors

• Wolrich Gilbert
• Bernstein Debra
• Cutter Daniel
• Dolan Christopher
• Adiletta Matthew J

Classifications

• G06F12/109

  for multiple virtual address spaces, e.g. segmentation (G06F12/1036 takes precedence) · CPC title

• G11C7/1072

  for memories with random access ports synchronised on clock signal pulse trains, e.g. synchronous memories, self timed memories · CPC title

• G06F3/0622

  in relation to access · CPC title

• G06F2212/1041

  Resource optimization · CPC title

• G06F15/17318

  Parallel communications techniques, e.g. gather, scatter, reduce, roadcast, multicast, all to all · CPC title