Memory mapping in a processor having multiple programmable units

Patent metadata

Field	Value
Publication number	US-9830284-B2
Application number	US-201514809423-A
Country	US
Kind code	B2
Filing date	Jul 27, 2015
Priority date	Dec 27, 1999
Publication date	Nov 28, 2017
Grant date	Nov 28, 2017

Abstract

The disclosure includes, in general, among other aspects, an apparatus having multiple programmable units integrated within a processor. The apparatus has circuitry to map addresses in a single address space to resources within the multiple programmable units where the single address space includes addresses for different ones of the resources in different ones of the multiple programmable units and where there is a one-to-one correspondence between respective addresses in the single address space and resources within the multiple programmable units.

First claim

What is claimed is:

1. A apparatus comprising:
a reduced instruction set computer (RISC) processor coupled to a first bus;
a multithreaded processor coupled to a second bus; and
translation logic coupled to the first bus and the second bus, the translation logic to translate a command of the RISC processor to access memory mapped registers of the multithreaded processor, wherein the translation logic comprises logic to convert a read or write command in a first format to a corresponding read or write command in a second format to enable the RISC processor to transfer data to and from the memory mapped registers of the multithreaded processor.

2. The apparatus of claim 1 , further comprising:
a synchronous dynamic random access memory (SDRAM) controller to couple to an SDRAM; and
a synchronous random access memory (SRAM) controller to couple to an SRAM.

3. The apparatus of claim 1 , wherein the multithreaded processor comprises:
controller logic including an instruction decoder and program counter units,
an arithmetic logic unit, and
a general purpose register set.

4. The apparatus of claim 1 , wherein the first bus is an internal core processor bus.

Assignees

• Intel Corp

Inventors

• Wolrich Gilbert
• Bernstein Debra
• Cutter Daniel
• Dolan Christopher
• Adiletta Matthew J

Classifications

• G06F12/109

  for multiple virtual address spaces, e.g. segmentation (G06F12/1036 takes precedence) · CPC title

• G06F12/0223

  User address space allocation, e.g. contiguous or non contiguous base addressing · CPC title

• G06F15/17318

  Parallel communications techniques, e.g. gather, scatter, reduce, roadcast, multicast, all to all · CPC title

• G11C7/1072

  for memories with random access ports synchronised on clock signal pulse trains, e.g. synchronous memories, self timed memories · CPC title

• G06F12/0284

  Multiple user address space allocation, e.g. using different base addresses (interprocessor communication G06F15/163) · CPC title