Memory mapping in a processor having multiple programmable units

Patent metadata

Field	Value
Publication number	US-2016019178-A1
Application number	US-201514809423-A
Country	US
Kind code	A1
Filing date	Jul 27, 2015
Priority date	Dec 27, 1999
Publication date	Jan 21, 2016
Grant date	—

Abstract

The disclosure includes, in general, among other aspects, an apparatus having multiple programmable units integrated within a processor. The apparatus has circuitry to map addresses in a single address space to resources within the multiple programmable units where the single address space includes addresses for different ones of the resources in different ones of the multiple programmable units and where there is a one-to-one correspondence between respective addresses in the single address space and resources within the multiple programmable units.

First claim

1 - 16 . (canceled)

17 . A apparatus comprising:
a reduced instruction set computer (RISC) processor coupled to a first bus; a multithreaded processor coupled to a second bus; and translation logic coupled to the first bus and the second bus, the translation logic to enable access to memory mapped registers of the multithreaded processor by the RISC processor.

18 . The apparatus of claim 17 , further comprising:
a synchronous dynamic random access memory (SDRAM) controller to couple to an SDRAM; and a synchronous random access memory (SRAM) controller to couple to an SRAM.

19 . The apparatus of claim 17 , wherein the multithreaded processor comprises controller logic, including an instruction decoder and program counter units, an arithmetic logic unit, a general purpose register set

20 . The apparatus of claim 17 , wherein the first bus is an AMBA bus.

21 . The apparatus of claim 17 , wherein the translation logic comprises logic to convert a read or write operation in a first format to a corresponding read or write operation in a second format.

Assignees

• Intel Corp

Inventors

• Wolrich Gilbert
• Bernstein Debra
• Cutter Daniel
• Dolan Christopher
• Adiletta Matthew J

Classifications

• G06F12/109

  for multiple virtual address spaces, e.g. segmentation (G06F12/1036 takes precedence) · CPC title

• G06F12/0806

  Multiuser, multiprocessor or multiprocessing cache systems · CPC title

• G06F12/06

  Addressing a physical block of locations, e.g. base addressing, module addressing, memory dedication (G06F12/08 takes precedence) · CPC title

• G06F15/76

  Architectures of general purpose stored program computers (with program plugboard G06F15/08; multicomputers G06F15/16) · CPC title

• G06F13/20 Primary

  for access to input/output bus · CPC title