Technologies for a distributed hardware queue manager

Patent metadata

Field	Value
Publication number	US-10216668-B2
Application number	US-201615087154-A
Country	US
Kind code	B2
Filing date	Mar 31, 2016
Priority date	Mar 31, 2016
Publication date	Feb 26, 2019
Grant date	Feb 26, 2019

Abstract

Technologies for a distributed hardware queue manager include a compute device having a processor. The processor includes two or more hardware queue managers as well as two or more processor cores. Each processor core can enqueue or dequeue data from the hardware queue manager. Each hardware queue manager can be configured to contain several queue data structures. In some embodiments, the queues are addressed by the processor cores using virtual queue addresses, which are translated into physical queue addresses for accessing the corresponding hardware queue manager. The virtual queues can be moved from one physical queue in one hardware queue manager to a different physical queue in a different physical queue manager without changing the virtual address of the virtual queue.

First claim

The invention claimed is:

1. A processor comprising:
a plurality of processor cores;
a plurality of hardware queue managers;
interconnect circuitry to connect each hardware queue manager of the plurality of hardware queue managers to each processor core of the plurality of processor cores; and
a plurality of queue mapping units, wherein each of the plurality of processor cores is associated with a different queue mapping unit of the plurality of queue mapping units and each of the plurality of queue mapping units is associated with a different processor core of the plurality of processor cores,
wherein each hardware queue manager of the plurality of hardware queue managers comprises:
enqueue circuitry to store data received from a processor core of the plurality of processor cores in a data queue associated with the respective hardware queue manager in response to an enqueue command generated by the processor core, wherein the enqueue command identifies the respective hardware queue manager;
dequeue circuitry to retrieve the data from the data queue associated with the respective hardware queue manager in response to a dequeue command generated by a processor core of the plurality of processor cores, wherein the dequeue command identifies the respective hardware queue manager; and

wherein each queue mapping unit of the plurality of queue mapping units is configured to:
receive a virtual queue address from the corresponding processor core;
translate the virtual queue address to a physical queue address; and
provide the physical queue address to the corresponding processor core.

2. The processor of claim 1 ,
wherein the enqueue command comprises a physical queue address of the respective hardware queue manager,
wherein to store the data comprises to add the data to a queue data structure in queue storage circuitry of the respective hardware queue manager based on the physical queue address,
wherein the dequeue command further comprises the physical queue address, and
wherein to retrieve the data from the data queue comprises to remove the data from the queue data structure of the queue storage circuitry based on the physical queue address.

3. The processor of claim 2 ,
wherein each hardware queue manager of the plurality of hardware queue managers further comprises a request buffer, wherein the request buffer is to:
store the data and the physical queue address in response to the enqueue command generated by the processor core before the data is stored by the enqueue circuitry
store the physical queue address in response to the dequeue command generated by the processor core before the data is retrieved by the dequeue circuitry.

4. The processor of claim 3 , wherein the enqueue circuitry of each of the plurality of hardware queue managers is further to:
determine, in response to the enqueue command, whether space is available in the request buffer; and
drop the enqueue command in response to a determination that there is not space available in the request buffer.

5. The processor of claim 1 , wherein each queue mapping unit of the plurality of queue mapping units comprises a queue translation lookaside buffer, wherein to translate the virtual queue address to the physical queue address comprises to:
determine whether a physical queue address corresponding to the virtual queue address is in the corresponding queue translation lookaside buffer;
access, in response to a determination that the physical queue address is not in the corresponding queue translation lookaside buffer, a queue mapping table in a memory associated with the processor for the physical queue address;
receive a response from the queue mapping table;
determine whether the response indicates the physical queue address;
update, in response to a determination that the response indicates the physical queue address, the queue translation lookaside buffer; and
provide, in response to a determination that the response does not indicate the physical queue address, an interrupt to the corresponding processor core.

6. The processor of claim 1 , wherein each hardware queue manager of the plurality of hardware queue managers further comprises queue migration circuitry to:
receive a signal indicating a queue migration, the signal comprising a source physical queue address of the hardware queue manager and a destination physical queue address of a destination hardware queue manager of the plurality of hardware queue managers; and
forward, in response to the signal, entries of a queue data structure associated with the source physical queue address to the destination hardware queue manager.

7. The processor of claim 1 , wherein:
the enqueue circuitry of each of the plurality of hardware queue managers is further to store additional data received from a hardware component different from the processor in the data queue in response to an additional enqueue command generated by the hardware component, wherein the additional enqueue command identifies the respective hardware queue manger of the plurality of hardware queue managers; and
the dequeue circuitry of each of the plurality of hardware queue managers is further to retrieve the additional data from the data queue in response to an additional dequeue command generated by the hardware component, wherein the additional dequeue command identifies the respective hardware queue manager of the plurality of hardware queue managers.

8. The processor of claim 1 , wherein the plurality of processor cores comprises at least 32 processor cores.

9. The processor of claim 1 , wherein each of the plurality of processor cores and each of the plurality of hardware queue managers are incorporated on a system-on-a-chip.

10. The processor of claim 9 , wherein a memory is incorporated on the system-on-a-chip.

11. A method for using a distributed hardware queue manager, the method comprising:
enqueuing queue data from a source processor core of a plurality of processor cores of a processor of a compute device to a target hardware queue manager of a plurality of hardware queue managers of the processor with use of a queue mapping unit of a plurality of queue mapping units, wherein each of the plurality of processor cores is associated with a different queue mapping unit of the plurality of queue mapping units and each of the plurality of queue mapping units is associated with a different processor core of the plurality of processor cores;
dequeuing the queue data from the target hardware queue manager to a destination processor core of the plurality of processor cores with use of the queue mapping unit of the plurality of queue mapping units; and
wherein each queue mapping unit of the plurality of queue mapping units is configured to:
receive a virtual queue address from the corresponding processor core;
translate the virtual queue address to a physical queue address; and
provide the physical queue address to the corresponding processor core.

12. The method of claim 11 , further comprising:
determining parameters for the target hardware queue manger, wherein the parameters indicate a size of an entry for each of a plurality of queue data structures of the target hardware queue manager; and
configuring the target hardware queue manager based on the parameters.

13. The method of claim 12 , wherein the parameters indicate a scheduling policy of the target hardware queue manager, wherein the scheduling policy of the target hardware queue manager indicates the order of execution for commands received by the target hardware queue manager.

14. The method of claim 12 , further comprising:
determining, for each

Assignees

• Intel Corp

Inventors

• Wang Ren
• Wang Yipeng
• Tsai Jr-Shian
• Herdrich Andrew
• Tai Tsung-Yuan
• Mcdonnell Niall
• Van Doren Stephen
• Sonnier David
• Bernstein Debra
• Wilkinson Hugh
• Vangati Narender
• Miller Stephen
• Eads Gage
• Cunningham Andrew
• Kenny Jonathan
• Richardson Bruce
• Burroughs William
• Hasting Joseph
• Yan An
• Clee James
• Ma Te
• Pirog Jerry
• Whitesell Jamison

Classifications

• G06F12/1027

  using associative or pseudo-associative address translation means, e.g. translation look-aside buffer [TLB] · CPC title

• G06F13/4004

  Coupling between buses · CPC title

• G06F2212/68

  Details of translation look-aside buffer [TLB] · CPC title

• G06F2212/50

  Control mechanisms for virtual memory, cache or TLB · CPC title

• G06F13/24

  using interrupt (G06F13/32 takes precedence) · CPC title