Memory thin provisioning using memory pools

Patent metadata

Field	Value
Publication number	US-12373335-B2
Application number	US-201916727595-A
Country	US
Kind code	B2
Filing date	Dec 26, 2019
Priority date	Dec 26, 2019
Publication date	Jul 29, 2025
Grant date	Jul 29, 2025

Abstract

Examples described herein relate to memory thin provisioning in a memory pool of one or more dual in-line memory modules or memory devices. At any instance, any central processing unit (CPU) can request and receive a full virtual allocation of memory in an amount that exceeds the physical memory attached to the CPU (near memory). A remote pool of additional memory can be dynamically utilized to fill the gap between allocated memory and near memory. This remote pool is shared between multiple CPUs, with dynamic assignment and address re-mapping provided for the remote pool. To improve performance, the near memory can be operated as a cache of the pool memory. Inclusive or exclusive content storage configurations can be applied. An inclusive cache configuration can include an entry in a near memory cache also being stored in a memory pool whereas an exclusive cache configuration can provide an entry in either a near memory cache or in a memory pool but not both. Near memory cache management includes current data location tracking, access counting and other caching heuristics, eviction of data from near memory cache to pool memory and movement of data from pool memory to memory cache.

First claim

What is claimed is:

1. An apparatus comprising:
an interface to a memory pool; and
at least one controller coupled to the interface to the memory pool, wherein memory allocations to two or more processors exceeds physical addressable memory allocated in the memory pool to the two or more processors, wherein multiple tenants share use of the memory pool, and wherein the at least one controller is to:
receive a first memory transaction request, the first memory transaction request comprising a first address and a first processor identifier and the first memory transaction request is received based on requested data associated with the first memory transaction request not stored in a near memory device coupled to at least one processor of the two or more processors;
translate the first address to a first physical address in the memory pool based on the first processor identifier;
receive a second memory transaction request, the second memory transaction request comprising the first address and a second processor identifier;
translate the first address to a second physical address in the memory pool based on the second processor identifier, wherein the first physical address is different than the second physical address and the first processor identifier is different than the second processor identifier; and
allocate a physical memory region in the memory pool in response to a write operation to the memory pool and wherein:
receipt of the first memory transaction request and the second memory transaction request is based on metadata accessed by a sender,
the metadata comprises a location indicator and the location indicator is to identify whether content associated with the first address is stored in the near memory device or the memory pool,
the metadata comprises a first access indicator to identify a number of accesses associated with the first address over an amount of time,
the sender is to access second metadata for a second address,
the second metadata comprises a location indicator to indicate whether content associated with the second address is stored in the near memory device or the memory pool,
the second metadata comprises a second access indicator to identify a number of accesses associated with the second address over an amount of time,
in response to a determination to evict content associated with a second address from the near memory device, the sender is to cause storage of content associated with the second address into the memory pool and update a location indicator of the second metadata to identify a location of content of the second address as being in the memory pool, and
based on the location indicator of the second metadata indicating that content associated with the second address is stored in the near memory device, the sender is to determine whether to evict content associated with the second address based on the first access indicator associated with the first address and the second access indicator associated with the second address.

2. The apparatus of claim 1 , further comprising multiple memory pools coupled to the at least one controller, wherein the memory pools provide redundant storage of content associated with the first address.

3. The apparatus of claim 1 , wherein the near memory device comprises one or more of: a cache and a volatile memory device.

4. The apparatus of claim 3 , wherein a strict subset of the near memory device is allocated for thin memory provisioning.

5. The apparatus of claim 1 , further comprising the memory pool.

6. The apparatus of claim 1 , further comprising the near memory device and the memory pool, wherein the at least one controller, the near memory device, and the memory pool are part of one or more of: a data center, rack, blade, or computing platform.

7. The apparatus of claim 1 , wherein in response to eviction of content associated with the second address from the near memory device, the sender is to cause storage of content into an available addressable region in the near memory device.

8. The apparatus of claim 1 , wherein:
a memory address value is allocated to multiple processors,
in a first mode, content associated with the memory address value is stored in both a memory and the memory pool, and
in a second mode, content associated with the memory address value is stored in the memory or in the memory pool but not both.

9. The apparatus of claim 1 , wherein at least one the two or more processors is to execute an operating system (OS) and the OS is to request utilization of memory within the physical addressable memory allocated in the memory pool and wherein the physical address memory allocated to the OS is less than the memory allocations to the two or more processors.

10. The apparatus of claim 1 , wherein the near memory device is communicatively coupled to the at least one processor of the two or more processors by a device interface and wherein the memory pool is coupled to the at least one controller by a network interface device.

11. The apparatus of claim 1 , wherein the memory pool consists of volatile memory.

12. At least one non-transitory computer readable medium, comprising instructions stored thereon, that if executed by one or more processors, cause the one or more processors to:
allocate less physical addressable memory in a near memory device and a memory pool to two or more processors than is allocated to the two or more processors, and
configure a controller to:
receive a first memory transaction request from at least one processor, the first memory transaction request comprising a first address and a first processor identifier and the first memory transaction request was received based on requested data associated with the first memory transaction request not being stored in the near memory device;
translate the first address to a first physical address in the memory pool based on the first processor identifier;
receive a second memory transaction request, the second memory transaction request comprising the first address and a second processor identifier;
translate the first address to a second physical address in the memory pool based on the second processor identifier, wherein the first physical address is different than the second physical address and the first processor identifier is different than the second processor identifier; and
allocate a physical memory region in the memory pool in response to a write operation to the memory pool, wherein:
receipt of the first memory transaction request and the second memory transaction request is based on metadata accessed by a sender,
the metadata comprises a location indicator and the location indicator is to identify whether content associated with the first address is stored in the near memory device or the memory pool,
the metadata comprises a first access indicator to identify a number of accesses associated with the first address over an amount of time,
the sender is to access second metadata for a second address,
the second metadata comprises a location indicator to indicate whether content associated with the second address is stored in the near memory device or the memory pool,
the second metadata comprises a second accesses indicator to identify a number of accesses associated with the second address over an amount of time,
in response to a determination to evict content associated with a second address from the near memory device, the sender is to cause storage of content associated with the second address into the memory pool and update a location indicator of the second metadata to identify a location of content of the second address as being in the memory pool, and
based on the locat

Assignees

• Intel Corp

Inventors

• Bernstein Debra
• Wilkinson Hugh
• Carrigan Douglas
• Coury Bassam N
• Adiletta Matthew J
• Srivastava Durgesh
• Warnes Lidia
• Wheeler William
• Fallon Michael F

Classifications

• G06F3/0604 Primary

  Improving or facilitating administration, e.g. storage management · CPC title

• G06F3/0685

  Hybrid storage combining heterogeneous device types, e.g. hierarchical storage, hybrid arrays · CPC title

• G06F3/0659

  Command handling arrangements, e.g. command buffers, queues, command scheduling · CPC title

• G06F3/0658

  Controller construction arrangements · CPC title

• G06F2212/1056

  Simplification · CPC title