Arbitrating memory accesses via a shared memory fabric

Patent metadata

Field	Value
Publication number	US-9535860-B2
Application number	US-201313743795-A
Country	US
Kind code	B2
Filing date	Jan 17, 2013
Priority date	Jan 17, 2013
Publication date	Jan 3, 2017
Grant date	Jan 3, 2017

Abstract

In an embodiment, a shared memory fabric is configured to receive memory requests from multiple agents, where at least some of the requests have an associated deadline value to indicate a maximum latency prior to completion of the memory request. Responsive to the requests, the fabric is to arbitrate between the requests based at least in part on the deadline values. Other embodiments are described and claimed.

First claim

What is claimed is:

1. An apparatus comprising:
a fabric coupled between a plurality of intellectual property (IP) blocks of a semiconductor device and a memory controller, the fabric configured to provide global timing information to at least some of the plurality of IP blocks and receive a plurality of memory requests from the plurality of IP blocks, wherein the fabric is configured to receive a memory request of the plurality of memory requests from a first IP block of the plurality of IP blocks, the memory request having a plurality of fields including a deadline field to provide a deadline value based at least in part on the global timing information, the deadline value communicated by the first IP block to indicate a maximum latency before completion of the memory request, the maximum latency determined by the first IP block and wherein the fabric is configured to arbitrate between the plurality of memory requests based at least in part on the deadline value included in the deadline field of the memory request.

2. The apparatus of claim 1 , wherein the fabric comprises:
an admit arbiter to receive the plurality of memory requests and to select one of the plurality of memory requests to provide to a memory scheduler arbiter; and
the memory scheduler arbiter coupled to the admit arbiter to select a first memory request from a group of memory requests to provide to the memory controller.

3. The apparatus of claim 2 , wherein the admit arbiter includes a first arbiter to receive memory requests from a first subset of the plurality of IP blocks and a first portion of the plurality of memory requests from a second subset of the plurality of IP blocks, and a second arbiter to receive a second portion of the plurality of memory requests from the second subset of the plurality of IP blocks.

4. The apparatus of claim 3 , wherein the second subset of the plurality of IP blocks comprise latency sensitive devices, the fabric to couple to the second subset of the plurality of IP blocks via a first interface and a second interface.

5. The apparatus of claim 4 , wherein the second arbiter is further to receive a deadline value included in each of the second portion of the plurality of memory requests received from the second subset of the plurality of IP blocks.

6. The apparatus of claim 3 , wherein the admit arbiter is controllable to operate in a first mode in which memory requests from the second arbiter are selected over memory requests from the first arbiter, and a second mode in which M memory requests from the first arbiter are selected after N memory requests from the second arbiter are selected, wherein M and N are obtained from a configuration register.

7. The apparatus of claim 3 , wherein the admit arbiter further includes a third arbiter coupled to an output of the first arbiter and the second arbiter and to arbitrate between the outputs of the first and second arbiters.

8. The apparatus of claim 2 , wherein the memory scheduler arbiter is to reorder the group of memory requests out of order based at least in part on address information of the memory requests.

9. The apparatus of claim 8 , wherein the memory scheduler arbiter is to reorder the group of memory requests out of order based at least in part on page hit status information associated with a memory request stored in an entry of a scoreboard of the fabric.

10. The apparatus of claim 1 , further comprising an interface logic coupled to a second IP block, the interface logic including a deadline logic to generate the deadline value based on a latency requirement for a first memory request of the second IP block and a global timer value of the global timing information provided from the fabric to the second IP block.

11. The apparatus of claim 10 , further comprising a deadline checker to receive the deadline value from the second IP block and to route the first memory request to a first arbiter or to a second arbiter based on the deadline value and a value of a global timer.

12. The apparatus of claim 1 , further comprising resource allocation logic to reserve virtual entries in a plurality of shared resources of the fabric for each of the plurality of IP blocks.

13. The apparatus of claim 12 , wherein the resource allocation logic is further to limit each of the plurality of IP blocks to a predetermined number of the plurality of shared resources.

14. The apparatus of claim 12 , wherein the plurality of shared resources includes a flush pool having a plurality of entries each to store a write request, wherein the resource allocation logic is to limit the plurality of entries to a flush limit, and wherein the admit arbiter is to block incoming write requests when a size of the flush pool equals the flush limit.

15. A method comprising:
receiving a memory request from a device of a plurality of devices coupled to a shared memory fabric of a system on chip (SoC), the memory request having a plurality of fields including a deadline field based at least in part on global timing information to provide a deadline value determined by the device, the deadline value to indicate a latency requirement for completion of the memory request, wherein the shared memory fabric provides the global timing information to at least some of the plurality of devices;
forwarding the memory request to a first arbiter of the shared memory fabric responsive to determining in the shared memory fabric that the deadline value is less than a latency threshold;
performing an arbitration in the first arbiter between a first plurality of memory requests including the memory request based at least in part on age values of the plurality of devices and forwarding a winner memory request of the first plurality of memory requests to a final arbiter of the shared memory fabric; and
performing a final arbitration in the final arbiter to select a final memory request for storage in a scoreboard of the shared memory fabric.

16. The method of claim 15 , further comprising:
forwarding the memory request to a second arbiter responsive to determining in the shared memory fabric that the deadline value is greater than the latency threshold;
performing an arbitration in the second arbiter between a second plurality of memory requests including the memory request based at least in part on the age values of the plurality of devices; and
forwarding a winner memory request of the second plurality of memory requests to the final arbiter.

17. The method of claim 15 , further comprising determining whether a weight value of a device associated with the final memory request equals a predetermined value, and if so updating the weight value to a configured value and updating the age values for others of the plurality of devices.

18. The method of claim 17 , further comprising when the weight value of the device associated with the final memory request does not equal the predetermined value, decrementing the weight value of the device associated with the final memory request.

19. The method of claim 15 , further comprising:
selecting via a memory scheduler of the shared memory fabric a memory request from the scoreboard for delivery to a memory controller; and
if a weight value of a device associated with the selected memory request equals a predetermined value, masking the device from further arbitration within the memory scheduler.

20. The method of claim 19 , further comprising determining whether a weight value of each of the plurality of devices equals the predetermined value and if so, updating the weight valu

Assignees

• Intel Corp

Inventors

• Cutter Daniel F
• Fanning Blaise
• Nagarajan Ramadass
• Niell Jose S
• Bernstein Debra
• Limaye Deepak
• Schoinas Ioannis T
• Iyer Ravishankar

Classifications

• G06F13/161

  with latency improvement · CPC title

• G06F13/1605

  based on arbitration (arbitration in handling access to a common bus or bus system G06F13/36) · CPC title

• G06F2213/0064

  Latency reduction in handling transfers · CPC title

• G06F13/1663 Primary

  Access to shared memory · CPC title

• G06F2212/1024

  Latency reduction · CPC title