Port landing-free low-skew signal distribution with backside metallization and buried rail
US-12598981-B2 · Apr 7, 2026 · US
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Badaroglu Mustafa patents
Badaroglu Mustafa is listed as an inventor on 70 patents in our database. Major assignees and classification codes are summarized below.
| Metric | Value |
|---|---|
| Inventor | Badaroglu Mustafa |
| Total patents | 70 |
| First publication | Sep 10, 2015 |
| Latest publication | Apr 7, 2026 |
Notable patents
Publications ranked by popularity score, then publication date.
Accumulator for digital computation-in-memory architectures
US-12541340-B2 · Feb 3, 2026 · US
Folding column adder architecture for digital compute in memory
US-12524372-B2 · Jan 13, 2026 · US
Partial sum management and reconfigurable systolic flow architectures for in-memory computation
US-12340304-B2 · Jun 24, 2025 · US
Trench power rail in cell circuits to reduce resistance and related power distribution networks and fabrication methods
US-12074109-B2 · Aug 27, 2024 · US
Digital compute in memory
US-12019905-B2 · Jun 25, 2024 · US
Port landing-free low-skew signal distribution with backside metallization and buried rail
US-2024096790-A1 · Mar 21, 2024 · US
Trench power rail in cell circuits to reduce resistance and related power distribution networks and fabrication methods
US-2023238325-A1 · Jul 27, 2023 · US
Accumulator for digital computation-in-memory architectures
US-2023115373-A1 · Apr 13, 2023 · US
Parallel depth-wise processing architectures for neural networks
US-2023065725-A1 · Mar 2, 2023 · US
Recent patents
Latest publications not already listed above.
Partial sum management and reconfigurable systolic flow architectures for in-memory computation
US-2023047364-A1 · Feb 16, 2023 · US
Digital compute-in-memory (DCIM) bit cell circuit layouts and DCIM arrays for multiple operations per column
US-11581037-B2 · Feb 14, 2023 · US
Folding column adder architecture for digital compute in memory
US-2023031841-A1 · Feb 2, 2023 · US
Digital compute in memory
US-2023037054-A1 · Feb 2, 2023 · US
Hybrid machine learning architecture with neural processing unit and compute-in-memory processing elements
US-2023025068-A1 · Jan 26, 2023 · US
Digital compute-in-memory (dcim) bit cell circuit layouts and dcim arrays for multiple operations per column
US-2022392524-A1 · Dec 8, 2022 · US
Hybrid metallization interconnects for power distribution and signaling
US-11121075-B2 · Sep 14, 2021 · US
Method of forming gate of semiconductor device and semiconductor device having same
US-10607896-B2 · Mar 31, 2020 · US
Integrated circuits employing varied gate topography between an active gate region(s) and a field gate region(s) in a gate(s) for reduced gate layout parasitic capacitance, and related methods
US-2020020688-A1 · Jan 16, 2020 · US
Integrated circuits (ics) made using extreme ultraviolet (euv) patterning and methods for fabricating such ics
US-2020006122-A1 · Jan 2, 2020 · US
Hybrid metallization interconnects for power distribution and signaling
US-2019295942-A1 · Sep 26, 2019 · US
Integrated circuits employing a field gate(s) without dielectric layers and/or work function metal layers for reduced gate layout parasitic resistance, and related methods
US-10411091-B1 · Sep 10, 2019 · US
Integrating a gate-all-around (GAA) field-effect transistor(s) (FET(S)) and a finFET(s) on a common substrate of a semiconductor die
US-10332881-B1 · Jun 25, 2019 · US
Standard cell circuits employing voltage rails electrically coupled to metal shunts for reducing or avoiding increases in voltage drop
US-10283526-B2 · May 7, 2019 · US
Digital current measurement for in-situ device monitoring
US-2019107569-A1 · Apr 11, 2019 · US
Nanowire device with reduced parasitics
US-2019067435-A1 · Feb 28, 2019 · US
Nanowire device with reduced parasitics
US-10157992-B2 · Dec 18, 2018 · US
Selectively recessing trench isolation in three-dimensional (3D) transistors to vary channel structure exposures from trench isolation to control drive strength
US-10109646-B1 · Oct 23, 2018 · US
Standard cell circuits employing high aspect ratio voltage rails for reduced resistance
US-10090244-B2 · Oct 2, 2018 · US
Semiconductor device having a gap defined therein
US-10079293-B2 · Sep 18, 2018 · US
Major assignees
Companies most often associated with this inventor's publications.
| Assignee | Patents |
|---|---|
| Qualcomm Inc | 67 |
| Imec Vzw | 2 |
| Qualcomm Incorporated | 1 |
Top CPC classifications
Most common classification codes across this inventor's patents.
| CPC | Patents |
|---|---|
| H10D84/038 | 26 |
| H10D64/017 | 25 |
| H10D30/62 | 18 |
| H10D30/024 | 17 |
| H10D89/10 | 15 |