Nanowire device with reduced parasitics

Patent metadata

Field	Value
Publication number	US-10157992-B2
Application number	US-201514980850-A
Country	US
Kind code	B2
Filing date	Dec 28, 2015
Priority date	Dec 28, 2015
Publication date	Dec 18, 2018
Grant date	Dec 18, 2018

Abstract

A nanowire transistor is provided that includes a well implant having a local isolation region for insulating a replacement metal gate from a parasitic channel. In addition, the nanowire transistor includes oxidized caps in the extension regions that inhibit parasitic gate-to-source and gate-to-drain capacitances.

First claim

We claim:

1. A nanowire transistor, comprising:
a nanowire extending from a first surface of a first extension region including a first semiconductor layer to a first surface of a second extension region including the first semiconductor layer, the first extension region and the second extension region each including a second semiconductor layer adjacent the first semiconductor layer;
a first spacer on the first surface of the first extension region;
a second spacer on the first surface of the second extension region; and
a replacement metal gate surrounding the nanowire, wherein the second semiconductor layer in the first extension region includes a first oxidized cap ending at the first surface of the first extension region and extending into the first extension region and the second semiconductor layer in the second extension region includes a second oxidized cap ending at the first surface of the second extension region and extending into the second extension region.

2. The nanowire transistor of claim 1 , further comprising:
a substrate; and
a well implant in the substrate adjacent the replacement metal gate, wherein the well implant includes an oxidized local isolation region positioned between a remainder of the well implant and the replacement metal gate.

3. The nanowire transistor of claim 1 , wherein each second semiconductor layer comprises a silicon germanium layer including an etch stop dopant.

4. The nanowire transistor of claim 3 , wherein the etch stop dopant comprises carbon.

5. The nanowire transistor of claim 1 , wherein the replacement metal gate comprises:
an outer high-k layer adjacent the at least one nanowire;
a metal gate fill;
and a work function layer between the outer high-k layer and the metal gate fill.

6. The nanowire transistor of claim 1 , further comprising:
a plurality of silicon nanowires, and wherein the second semiconductor layer in the first extension region and the second semiconductor layer in the second extension region each comprises a plurality of silicon germanium layers.

7. The nanowire transistor of claim 1 , wherein each second semiconductor layer comprises a silicon layer including an etch stop dopant.

Assignees

• Qualcomm Inc

Inventors

• Badaroglu Mustafa
• Machkaoutsan Vladimir
• Song Stanley Seungchul
• Xu Jeffrey Junhao
• Nowak Matthew Michael
• Yeap Choh Fei

Classifications

• H10P14/3411

  Silicon, silicon germanium or germanium · CPC title

• H10P14/3252

  Alternating layers, e.g. superlattice · CPC title

• H10W10/011

  of isolation regions comprising dielectric materials · CPC title

• H10W10/10

  Isolation regions comprising dielectric materials · CPC title

• B82Y10/00

  Nanotechnology for information processing, storage or transmission, e.g. quantum computing or single electron logic · CPC title