Standard cell circuits employing voltage rails electrically coupled to metal shunts for reducing or avoiding increases in voltage drop

Patent metadata

Field	Value
Publication number	US-10283526-B2
Application number	US-201615386501-A
Country	US
Kind code	B2
Filing date	Dec 21, 2016
Priority date	Dec 21, 2016
Publication date	May 7, 2019
Grant date	May 7, 2019

Abstract

Standard cell circuits employing voltage rails electrically coupled to metal shunts for reducing or avoiding increases in voltage drop are disclosed. In one aspect, a standard cell circuit is provided that employs active devices that include corresponding gates disposed with a gate pitch. First and second voltage rails having a line width are disposed in a first metal layer. Employing the first and second voltage rails having substantially a same line width reduces the height of the standard cell circuit as compared to conventional standard cell circuits. Metal lines are disposed in a second metal layer with a metal pitch less than the gate pitch such that the number of metal lines exceeds the number of gates. Electrically coupling the first and second voltage rails to the metal shunts increases the conductive area of each voltage rail, which reduces a voltage drop across each voltage rail.

First claim

What is claimed is:

1. A standard cell circuit, comprising:
a plurality of active devices comprising a plurality of corresponding gates disposed with a gate pitch;
a first voltage rail having a line width disposed in a first metal layer and corresponding to a first one-half track, wherein the first voltage rail is configured to receive a first voltage;
a second voltage rail having the line width disposed in the first metal layer and corresponding to a second one-half track, wherein the second voltage rail is configured to receive a second voltage;
a plurality of metal lines disposed in a second metal layer with a metal pitch less than the gate pitch, wherein one or more metal lines of the plurality of metal lines is electrically coupled to one or more gates of the plurality of gates;
a first metal shunt disposed in a third metal layer and electrically coupled to the first voltage rail and one or more metal lines of the plurality of metal lines not electrically coupled to the one or more gates;
a second metal shunt disposed in the third metal layer and electrically coupled to the second voltage rail and one or more metal lines of the plurality of metal lines not electrically coupled to the one or more gates; and
a plurality of routing lines disposed in the first metal layer between the first voltage rail and the second voltage rail, wherein each routing line has substantially a same line width as the first voltage rail and the second voltage rail, and each routing line corresponds to a routing track of a plurality of routing tracks.

2. The standard cell circuit of claim 1 , further comprising:
one or more first vias disposed between the first metal layer and the second metal layer, wherein each of the one or more first vias electrically couples the first voltage rail to one or more corresponding metal lines; and
one or more second vias disposed between the first metal layer and the second metal layer, wherein each of the one or more second vias electrically couples the second voltage rail to one or more corresponding metal lines.

3. The standard cell circuit of claim 2 , further comprising:
one or more first vias disposed between the second metal layer and the third metal layer, wherein each of the one or more first vias electrically couples one or more corresponding metal lines to the first metal shunt; and
one or more second vias disposed between the second metal layer and the third metal layer, wherein each of the one or more second vias electrically couples one or more corresponding metal lines to the second metal shunt.

4. The standard cell circuit of claim 1 , wherein the metal pitch is approximately equal to two-thirds (⅔) of the gate pitch.

5. The standard cell circuit of claim 4 , wherein:
the metal pitch is approximately equal to twenty-eight (28) nanometers (nm); and
the gate pitch is approximately equal to forty-two (42) nm.

6. The standard cell circuit of claim 1 , wherein the metal pitch is between approximately one-half (½) and three-fourths (¾) of the gate pitch.

7. The standard cell circuit of claim 6 , wherein:
the metal pitch is between approximately twenty (20) nm and thirty (30) nm; and
the gate pitch is between approximately forty (40) nm and forty-two (42) nm.

8. The standard cell circuit of claim 1 , wherein the plurality of routing tracks comprises four (4) tracks.

9. The standard cell circuit of claim 1 , wherein:
the second metal layer is disposed between the first metal layer and the third metal layer; and
the third metal layer is disposed above the second metal layer.

10. The standard cell circuit of claim 9 , wherein the first metal layer comprises a metal zero (M0) metal layer.

11. The standard cell circuit of claim 10 , wherein the second metal layer comprises a metal one (M1) metal layer.

12. The standard cell circuit of claim 11 , wherein the third metal layer comprises a metal two (M2) metal layer.

13. The standard cell circuit of claim 1 , wherein the line width is approximately equal to a minimum line width.

14. The standard cell circuit of claim 1 , further comprising a technology node size equal to approximately ten (10) nanometers (nm).

15. The standard cell circuit of claim 1 integrated into an integrated circuit (IC).

16. The standard cell circuit of claim 1 integrated into a device selected from the group consisting of: a set top box; an entertainment unit; a navigation device; a communications device; a fixed location data unit; a mobile location data unit; a global positioning system (GPS) device; a mobile phone; a cellular phone; a smart phone; a session initiation protocol (SIP) phone; a tablet; a phablet; a server; a computer; a portable computer; a mobile computing device; a wearable computing device; a desktop computer; a personal digital assistant (PDA); a monitor; a computer monitor; a television; a tuner; a radio; a satellite radio; a music player; a digital music player; a portable music player; a digital video player; a video player; a digital video disc (DVD) player; a portable digital video player; an automobile; a vehicle component; avionics systems; a drone; and a multicopter.

17. A standard cell circuit, comprising:
a means for performing a logic function comprising a means for receiving a gate voltage disposed with a gate pitch;
a means for providing a first voltage disposed in a first metal layer having a line width and corresponding to a first one-half track;
a means for providing a second voltage disposed in the first metal layer having the line width and corresponding to a second one-half track;
a plurality of means for electrically coupling disposed in a second metal layer with a metal pitch less than the gate pitch, wherein one or more means for electrically coupling is electrically coupled to the means for receiving the gate voltage;
a means for increasing a first resistance disposed in a third metal layer electrically coupled to the means for providing the first voltage and one or more means for electrically coupling not electrically coupled to the means for receiving the gate voltage;
a means for increasing a second resistance disposed in the third metal layer electrically coupled to the means for providing the second voltage and one or more means for electrically coupling not electrically coupled to the means for receiving the gate voltage; and
a plurality of means for routing disposed in the first metal layer between the means for providing the first voltage and the means for providing the second voltage, wherein each of the means for routing has substantially a same line width as the means for providing the first voltage and the means for providing the second voltage, and each of the means for routing corresponds to a routing track of a plurality of routing tracks.

18. The standard cell circuit of claim 17 , further comprising:
a means for interconnecting the means for providing the first voltage to the one or more means for electrically coupling; and
a means for interconnecting the means for providing the second voltage to the one or more means for electrically coupling.

19. The standard cell circuit of claim 18 , further comprising:
a means for interconnecting the one or more means for electrically coupling to the means for increasing the first resistance; and
a means for interconnecting the one or more means for electrically coupling to the means for increasing the second resistance.

20. The standard cell circuit of claim 17 , wherein the metal pitch is approximately equal to two-thirds of the gate pitch.

Assignees

• Qualcomm Inc

Inventors

• Zhu John Jianhong
• Xu Jeffrey Junhao
• Badaroglu Mustafa

Classifications

• H10W72/00

  Interconnections or connectors in packages · CPC title

• H10W70/611

  for connecting multiple chips together · CPC title

• H10W70/65

  Shapes or dispositions of interconnections · CPC title

• H10W20/427

  Power or ground buses · CPC title

• H01L21/823475

  Electricity · mapped topic