Selectively recessing trench isolation in three-dimensional (3D) transistors to vary channel structure exposures from trench isolation to control drive strength

Patent metadata

Field	Value
Publication number	US-10109646-B1
Application number	US-201715613656-A
Country	US
Kind code	B1
Filing date	Jun 5, 2017
Priority date	Jun 5, 2017
Publication date	Oct 23, 2018
Grant date	Oct 23, 2018

Abstract

Selectively recessing trench isolation in three-dimensional (3D) transistors to vary channel structure exposures from trench isolation to control drive strength is disclosed. The ability to vary the exposures of channel structures in 3D transistors from trench isolation allows the drive strengths of the 3D transistors to be varied. Varying the drive strengths of 3D transistors may be advantageous in certain circuit applications to reduce power consumption and/or control drive strength ratios between transistors, as examples. In this regard, in exemplary aspects disclosed herein, during the fabrication of 3D transistors, a trench isolation material is disposed adjacent to channel structures formed from a substrate. The amount of trench isolation material disposed adjacent to each channel structure determines the amount of channel structure surface area exposed to a gate. The amount of channel structure surface area of the 3D transistor exposed to the gate affects the drive strength of the 3D transistor.

First claim

What is claimed is:

1. An integrated circuit (IC), comprising:
a substrate comprising a substantially planar top surface;
a first three-dimensional (3D) transistor, comprising:
a first channel structure extending from the substantially planar top surface of the substrate to a first channel structure height above the substantially planar top surface, the first channel structure comprising a first end portion, a second end portion, a first side surface, and a second side surface opposite the first side surface;
a first source formed in the first end portion of the first channel structure;
a first drain formed in the second end portion of the first channel structure;
at least one first channel formed in the first channel structure between the first source and the first drain;
a first trench isolation layer disposed above the substrate and laterally adjacent to the first channel structure, the first trench isolation layer comprising a substantially planar top surface at a first trench isolation height above the substantially planar top surface of the substrate; and
a first gate disposed over at least a portion of the first side surface and a portion of the second side surface, and above the first trench isolation layer to a gate height above the substantially planar top surface of the substrate; and

a second 3D transistor, comprising:
a second channel structure extending from the substantially planar top surface of the substrate to a second channel structure height above the substantially planar top surface substantially the same as the first channel structure height, the second channel structure comprising a first end portion, a second end portion, a third side surface, and a fourth side surface opposite the third side surface;
a second source formed in the first end portion of the second channel structure;
a second drain formed in the second end portion of the second channel structure;
at least one second channel formed in the second channel structure between the second source and the second drain;
a second trench isolation layer disposed above the substrate and laterally adjacent to the second channel structure, the second trench isolation layer comprising a substantially planar top surface at a second trench isolation height above the substantially planar top surface of the substrate different from the first trench isolation height; and
a second gate disposed over at least a portion of the third side surface and a portion of the fourth side surface, and above the second trench isolation layer to the gate height;

the at least one first channel of the first 3D transistor doped with a first dopant of a first polarity; and
the at least one second channel of the second 3D transistor doped with a second dopant of a second polarity opposite that of the first polarity.

2. The IC of claim 1 , wherein the first 3D transistor has a first drive strength and the second 3D transistor has a second drive strength different from the first drive strength.

3. The IC of claim 2 , wherein the first drive strength is a function of the first trench isolation height and the second drive strength is a function of the second trench isolation height.

4. The IC of claim 1 , further comprising:
a third 3D transistor, comprising:
a third channel structure extending from the substantially planar top surface of the substrate to a third channel structure height above the substantially planar top surface substantially the same as the first channel structure height, the third channel structure comprising a first end portion, a second end portion, a fifth side surface, and a sixth side surface opposite the fifth side surface;
a third source formed in the first end portion of the third channel structure;
a third drain formed in the second end portion of the third channel structure;
at least one third channel formed in the third channel structure between the third source and the third drain;
a third trench isolation layer disposed above the substrate and laterally adjacent to the third channel structure, the third trench isolation layer comprising a substantially planar top surface at a third trench isolation height above the substantially planar top surface of the substrate different from the first trench isolation height and the second trench isolation height; and
a third gate disposed over at least a portion of the fifth side surface and a portion of the sixth side surface, and above the third trench isolation layer to the gate height.

5. The IC of claim 1 , further comprising:
a complementary metal-oxide semiconductor (CMOS) standard cell;
wherein the first 3D transistor and the second 3D transistor are integrated into the CMOS standard cell.

6. The IC of claim 5 , wherein:
the at least one first channel of the first 3D transistor is doped with a first dopant of a first polarity; and
the at least one second channel of the second 3D transistor is doped with a second dopant of a second polarity opposite that of the first polarity.

7. The IC of claim 1 , further comprising:
a third 3D transistor, comprising:
a third channel structure extending from the substantially planar top surface of the substrate to a third channel structure height above the substantially planar top surface substantially the same as the first channel structure height, the third channel structure comprising a first end portion, a second end portion, a fifth side surface, and a sixth side surface opposite the fifth side surface;
a third source formed in the first end portion of the third channel structure;
a third drain formed in the second end portion of the third channel structure;
at least one third channel formed in the third channel structure between the third source and the third drain;
a third trench isolation layer disposed above the substrate and laterally adjacent to the third channel structure; and
a third gate disposed over at least a portion of the fifth side surface and a portion of the sixth side surface, and above the third trench isolation layer to the gate height;

a fourth 3D transistor, comprising:
a fourth channel structure extending from the substantially planar top surface of the substrate to a fourth channel structure height above the substantially planar top surface substantially the same as the first channel structure height, the fourth channel structure comprising a first end portion, a second end portion, a seventh side surface, and an eighth side surface opposite the seventh side surface;
a fourth source formed in the first end portion of the fourth channel structure;
a fourth drain formed in the second end portion of the fourth channel structure;
at least one fourth channel formed in the fourth channel structure between the fourth source and the fourth drain;
a fourth trench isolation layer disposed above the substrate and laterally adjacent to the fourth channel structure; and
a fourth gate disposed over at least a portion of the seventh side surface and a portion of the eighth side surface, and above the fourth trench isolation layer to the gate height;

a first complementary metal-oxide semiconductor (CMOS) standard cell;
wherein the first 3D transistor and the third 3D transistor are integrated into the first CMOS standard cell; and

a second CMOS standard cell;
wherein the second 3D transistor and the fourth 3D transistor are integrated into the second CMOS standard cell.

8. The IC of claim 7 , wherein:
the third trench isolation layer further comprises a substantially planar top surface at the first trench isolation height above the substantially planar top surface of the substrate; and
the fourth trench isolation layer further comprises a substantially planar top surface at the second trench isolation height above the

Assignees

• Qualcomm Inc

Inventors

• Badaroglu Mustafa

Classifications

• H01L2027/11824

  Electricity · mapped topic

• H01L27/11807 Primary

  Electricity · mapped topic

• H10D84/851

  comprising IGFETs having stacked nanowire, nanosheet or nanoribbon channels · CPC title

• H10D84/853

  comprising FinFETs · CPC title

• H10D84/924

  for current drive capability · CPC title