Semiconductor device having a gap defined therein

Patent metadata

Field	Value
Publication number	US-10079293-B2
Application number	US-201715839050-A
Country	US
Kind code	B2
Filing date	Dec 12, 2017
Priority date	Mar 10, 2014
Publication date	Sep 18, 2018
Grant date	Sep 18, 2018

Abstract

A method includes forming a first spacer structure on a dummy gate of a semiconductor device and forming a sacrificial spacer on the first spacer structure. The method also includes etching a structure of the semiconductor device to create an opening, removing the sacrificial spacer via the opening, and depositing a material to close to define a gap.

First claim

What is claimed is:

1. A method of forming a semiconductor device, the method comprising:
forming a first spacer structure on a dummy gate;
forming a sacrificial spacer on the first spacer structure;
etching a portion of a fin to create an opening; and
removing the sacrificial spacer via the opening and depositing a material to close the opening to define a gap.

2. The method of claim 1 , wherein etching the portion of the fin exposes a portion of the sacrificial spacer.

3. The method of claim 1 , wherein the gap is further defined by a sidewall of the first spacer structure, the sidewall of the first spacer structure in contact with the dummy gate.

4. The method of claim 1 , wherein etching the portion of the fin includes etching a structure that includes the first spacer structure, a second spacer structure, or both, and wherein etching the structure includes removing a portion of the first spacer structure, a portion of the second spacer structure, or a combination thereof.

5. The method of claim 4 , wherein the material corresponds to a third spacer structure, wherein the third spacer structure is in contact with the first spacer structure, the second spacer structure, or both.

6. The method of claim 5 , wherein a spacer of the semiconductor device comprises the first spacer structure, the second spacer structure, and the third spacer structure.

7. The method of claim 1 , wherein the material corresponds to a source/drain region material of a source/drain region of the semiconductor device, and wherein depositing the material comprises epitaxially growing the source/drain region of the semiconductor device.

8. The method of claim 1 , wherein the opening is defined by the first spacer structure, a second spacer structure, a dielectric layer, the dummy gate, or a combination thereof.

9. The method of claim 1 , further comprising replacing the dummy gate with a gate, and wherein the opening is defined by the first spacer structure, a second spacer structure, a dielectric layer, the gate, or a combination thereof.

10. The method of claim 1 , further comprising forming a second spacer structure on the sacrificial spacer.

11. The method of claim 10 , wherein a portion of the second spacer structure is formed on a portion of the first spacer structure.

12. The method of claim 10 , wherein a portion of the material is positioned between the first spacer structure and the second spacer structure.

13. The method of claim 10 , wherein the first spacer structure includes a first material, and wherein the second spacer structure includes the first material.

14. The method of claim 10 , wherein a spacer of the semiconductor device comprises the first spacer structure and the second spacer structure.

15. A non-transitory computer-readable medium comprising processor-executable instructions that, when executed by a processor, cause the processor to:
initiate formation of a semiconductor device, the semiconductor device formed by:
forming a first spacer structure on a dummy gate;
forming a sacrificial spacer on the first spacer structure;
etching a portion of a fin to create an opening; and
removing the sacrificial spacer via the opening and depositing a material to close the opening to define a gap.

16. The non-transitory computer-readable medium of claim 15 , wherein the semiconductor device is further formed by:
forming the dummy gate on a substrate of the semiconductor device;
removing the dummy gate to create a cavity; and
forming a gate in the cavity, wherein the gate is coupled to a channel region of the semiconductor device.

17. The non-transitory computer-readable medium of claim 16 , wherein the channel region is included in the fin of the substrate.

18. The non-transitory computer-readable medium of claim 16 , wherein the dummy gate is removed prior to removing the sacrificial spacer.

19. The non-transitory computer-readable medium of claim 16 , wherein the sacrificial spacer is removed prior to removing the dummy gate.

20. The non-transitory computer-readable medium of claim 16 , wherein the semiconductor device is further formed by forming a contact subsequent to forming the gate, wherein the contact is electrically coupled to a source/drain region of the semiconductor device.

21. The non-transitory computer-readable medium of claim 15 , wherein the semiconductor device is further formed by:
forming a source/drain region on a substrate of the semiconductor device;
forming a dielectric layer on the source/drain region;
removing a portion of the dielectric layer to create a cavity; and
forming a contact in the cavity, wherein the contact is electrically coupled to the source/drain region.

22. The non-transitory computer-readable medium of claim 21 , wherein the contact is formed prior to removing the sacrificial spacer.

23. The non-transitory computer-readable medium of claim 21 , wherein the sacrificial spacer is removed prior to forming the contact.

Assignees

• Qualcomm Inc

Inventors

• Xu Jeffrey Junhao
• Rim Kern
• Zhu John Jianhong
• Song Stanley Seungchul
• Badaroglu Mustafa
• Machkaoutsan Vladimir
• Yang Da
• Yeap Choh Fei

Classifications

• H01L29/4991

  Electricity · mapped topic

• H01L29/785

  Electricity · mapped topic

• H01L29/66795

  Electricity · mapped topic

• H01L29/66545

  Electricity · mapped topic

• H01L29/6653

  Electricity · mapped topic