Digital compute in memory

Patent metadata

Field	Value
Publication number	US-12019905-B2
Application number	US-202217816285-A
Country	US
Kind code	B2
Filing date	Jul 29, 2022
Priority date	Aug 2, 2021
Publication date	Jun 25, 2024
Grant date	Jun 25, 2024

Abstract

Certain aspects generally relate to performing machine learning tasks, and in particular, to computation-in-memory architectures and operations. One aspect provides a circuit for in-memory computation. The circuit generally includes multiple bit-lines, multiple word-lines, an array of compute-in-memory cells, and a plurality of accumulators, each accumulator being coupled to a respective one of the multiple bit-lines. Each compute-in-memory cell is coupled to one of the bit-lines and to one of the word-lines and is configured to store a weight bit of a neural network.

First claim

What is claimed is:

1. A circuit comprising:
multiple bit-lines;
multiple word-lines;
an array of compute-in-memory cells, wherein each compute-in-memory cell is coupled to one of the bit-lines and to one of the word-lines and is configured to store a weight bit of a neural network;
a plurality of accumulators, each accumulator being coupled to a respective one of the multiple bit-lines; and
a plurality of sense amplifiers, each sense amplifier having an output coupled to a respective one of the accumulators and having an input coupled to the respective one of the multiple bit-lines,
wherein the plurality of sense amplifiers are configured to concurrently sense the multiple bit-lines on a bit-line basis,
wherein the multiple word-lines are configured to be activated one word-line at a time for each computational cycle, and
wherein the number of computation cycles corresponds to the number of activation inputs and is an indication of the amount of time it takes to receive accumulation results for the activation inputs.

2. The circuit of claim 1 , wherein the compute-in-memory cells coupled to the multiple bit-lines and to one of the multiple word-lines are configured to perform concurrent computations.

3. The circuit of claim 1 , wherein:
two or more of the word-lines are configured to be sequentially activated; and
each of the plurality of accumulators is configured to accumulate output signals from the compute-in-memory cells coupled to the respective one of the multiple bit-lines after the two or more of the word-lines are sequentially activated.

4. The circuit of claim 3 , wherein the output signals comprise digital signals generated by the compute-in-memory cells on the respective one of the multiple bit-lines.

5. The circuit of claim 3 , further comprising control circuitry configured to select the two or more of the word-lines that are sequentially activated based on an activation input applied to each of the two or more of the word-lines being logic high.

6. The circuit of claim 1 , wherein each of the plurality of accumulators is configured to perform accumulation of output signals from the compute-in-memory cells coupled to the respective one of the multiple bit-lines, and wherein, in performing the accumulation, each of the plurality of accumulators is configured to:
accumulate output signals from two or more of the compute-in-memory cells; and
skip accumulation of at least one output signal from at least one other compute-in-memory cell coupled to the respective one of the multiple bit-lines, based on the at least one other compute-in-memory cell receiving an activation input that is logic low.

7. The circuit of claim 1 , wherein each compute-in-memory cell is configured to multiply the stored weight bit with an activation input provided to a respective one of the multiple word-lines.

8. The circuit of claim 1 , wherein:
the compute-in-memory cells coupled to each of the multiple word-lines are configured to be sequentially activated based on a plurality of activation inputs applied to the multiple word-lines; and
a respective one of the plurality of accumulators is configured to accumulate output signals from the compute-in-memory cells after the compute-in-memory cells coupled to each of the multiple word-lines are sequentially activated.

9. The circuit of claim 8 , wherein:
the respective one of the plurality of accumulators is configured to accumulate the output signals after multiple activation cycles; and
during each of the multiple activation cycles, a respective one of the activation inputs that is logic high is provided to a respective one of the multiple word-lines.

10. The circuit of claim 1 , wherein each compute-in-memory cell comprises:
a pass-gate transistor;
a cross-coupled invertor pair having an output coupled to the pass-gate transistor;
a first transistor having a gate coupled to the output of the cross-coupled invertor pair; and
a second transistor coupled between the first transistor and the respective one of the multiple bit-lines.

11. The circuit of claim 10 , wherein the first transistor comprises a source coupled to a reference potential node and a drain coupled to a source of the second transistor and wherein a drain of the second transistor is coupled to the respective one of the multiple bit-lines.

12. The circuit of claim 10 , wherein a gate of the second transistor is coupled to a respective one of the multiple word-lines.

13. The circuit of claim 1 , wherein at least one of the compute-in-memory cells comprises an eight-transistor (8T) static random access memory (SRAM) cell.

14. A method comprising:
performing computations, in at least a portion of an array of compute-in-memory cells, on a weight and an activation input for a neural network, each compute-in-memory cell being coupled to one of multiple bit-lines and to one of multiple word-lines and being configured to store a bit of the weight for the neural network;
accumulating, via each accumulator of a plurality of accumulators, output signals from two or more of the compute-in-memory cells coupled to a respective one of the multiple bit-lines;
sensing, via each sense amplifier of a plurality of sense amplifiers, the respective one of the multiple bit-lines, wherein the output signals from the two or more of the compute-in-memory cells are accumulated based on the sensing of the respective one of the multiple bit-lines; and
sequentially activating two or more of the word-lines, wherein the accumulating occurs after the sequentially activating and wherein the sequentially activating comprises applying the activation input to each of the two or more word-lines, one word-line at a time for each computational cycle,
wherein the sensing comprises concurrently sensing the multiple bit-lines via the plurality of sense amplifiers on a bit-line basis, and
wherein the number of computation cycles corresponds to the number of activation inputs and is an indication of the amount of time it takes to receive accumulation results for the activation inputs.

15. The method of claim 14 , wherein the output signals comprise digital signals generated by the compute-in-memory cells on the respective one of the multiple bit-lines.

16. The method of claim 14 , further comprising sequentially activating two or more of the word-lines, wherein the accumulating occurs after the sequentially activating and wherein the sequentially activating comprises applying the activation input to each of the two or more word-lines, one word-line at a time.

17. The method of claim 16 , further comprising selecting the two or more word-lines that are sequentially activated based on the activation input applied to each of the two or more word-lines being logic high.

18. The method of claim 14 , further comprising skipping accumulating of at least one output signal from at least one other compute-in-memory cell in the array of compute-in-memory cells based on the at least one other compute-in-memory cell receiving the activation input, which is logic low.

19. The method of claim 14 , wherein performing the computations comprises multiplying, via each of the compute-in-memory cells coupled to a respective one of the multiple word-lines in the at least the portion of the array, the bits of the weight with the activation input provided to the respective one of the multiple word-lines.

20. The method of claim 14 , wherein:
the output signals are accumulated, via a respective one of the plurality of accumulators, after multiple activatio

Assignees

• Qualcomm Inc

Inventors

• Wang Zhongze
• Badaroglu Mustafa

Classifications

• G06F3/0604

  Improving or facilitating administration, e.g. storage management · CPC title

• G06F3/0679

  Non-volatile semiconductor memory device, e.g. flash memory, one time programmable memory [OTP] · CPC title

• G06F2207/4824

  Neural networks · CPC title

• G06N3/09

  Supervised learning · CPC title

• G11C11/419

  Read-write [R-W] circuits · CPC title