Nonvolatile semiconductor memory device and method of manufacturing the same
US-9837264-B2 · Dec 5, 2017 · US
with a control gate layer also being used as part of the peripheral transistor
with a control gate layer also being used as part of the peripheral transistor · Cooperative Patent Classification (CPC)
Electric circuits, power, telecommunications, and semiconductors.
Related technology areas
Mapped technology topics for this CPC code.
| Metric | Value |
|---|---|
| CPC code | H10B41/44 |
| Official title | with a control gate layer also being used as part of the peripheral transistor |
| Display label | with a control gate layer also being used as part of the peripheral transistor |
| Total patents | 216 |
Filing trend
Year-over-year patent counts classified under this CPC code.
Filing activity over the last five years is rapidly declining.
| Year | Patents |
|---|---|
| 2015 | 19 |
| 2016 | 20 |
| 2017 | 35 |
| 2018 | 22 |
| 2019 | 22 |
| 2020 | 34 |
| 2021 | 25 |
| 2022 | 16 |
| 2023 | 12 |
| 2024 | 5 |
| 2025 | 6 |
Representative patents
Representative publications under this CPC code from precomputed stats, or recent filings when stats are unavailable.
Method for Forming a PN Junction and Associated Semiconductor Device
US-2017345836-A1 · Nov 30, 2017 · US
Nvm memory hkmg integration technology
US-2017345841-A1 · Nov 30, 2017 · US
Soi memory device
US-2017345834-A1 · Nov 30, 2017 · US
Semiconductor device and method of forming the same
US-9812327-B2 · Nov 7, 2017 · US
Nonvolatile memory device and method for manufacturing the same
US-2017221914-A1 · Aug 3, 2017 · US
Semiconductor device and method of fabricating semiconductor device
US-2017221913-A1 · Aug 3, 2017 · US
Method of forming self-aligned split-gate memory cell array with metal gates and logic devices
US-9721958-B2 · Aug 1, 2017 · US
Non-volatile memory having individually optimized silicide contacts and process therefor
US-2017207092-A1 · Jul 20, 2017 · US
Electronic chip manufacturing method
US-2017200730-A1 · Jul 13, 2017 · US
Methods and structures for a split gate memory cell structure
US-2017194444-A1 · Jul 6, 2017 · US
Method of forming memory array and logic devices
US-9673208-B2 · Jun 6, 2017 · US
Semiconductor device and method of fabricating the same
US-9627247-B2 · Apr 18, 2017 · US
Method Of Making Embedded Memory Device With Silicon-On-Insulator Substrate
US-2017103989-A1 · Apr 13, 2017 · US
Method of forming memory array and logic devices
US-2017103991-A1 · Apr 13, 2017 · US
Semiconductor device and method of forming the same
US-2017062444-A1 · Mar 2, 2017 · US
Method including a formation of a control gate of a nonvolatile memory cell and semiconductor structure
US-9583640-B1 · Feb 28, 2017 · US
Semiconductor structure including a nonvolatile memory cell and method for the formation thereof
US-2017047336-A1 · Feb 16, 2017 · US
Nonvolatile semiconductor memory device and method of manufacturing the same
US-2017018558-A1 · Jan 19, 2017 · US
Method for manufacturing a nonvolatile memory device
US-2017018559-A1 · Jan 19, 2017 · US
Frequently asked questions
Answers are generated from the same data shown on this page.
- What is CPC H10B41/44?
- CPC H10B41/44 is the Cooperative Patent Classification code for “with a control gate layer also being used as part of the peripheral transistor.”
- How many patents are filed under CPC H10B41/44 (with a control gate layer also being used as part of the peripheral transistor)?
- Our database includes 216 publications tagged with this CPC code.
- Is patent activity under CPC H10B41/44 growing?
- Publication counts under this code: 5 in 2024 vs 6 in 2025 (latest complete years).