Method of forming self-aligned split-gate memory cell array with metal gates and logic devices

Patent metadata

Field	Value
Publication number	US-9721958-B2
Application number	US-201615003659-A
Country	US
Kind code	B2
Filing date	Jan 21, 2016
Priority date	Jan 23, 2015
Publication date	Aug 1, 2017
Grant date	Aug 1, 2017

Abstract

A method of forming a memory device by forming spaced apart first and second regions with a channel region therebetween, forming a floating gate over and insulated from a first portion of the channel region, forming a control gate over and insulated from the floating gate, forming an erase gate over and insulated from the first region, and forming a select gate over and insulated from a second portion of the channel region. Forming of the floating gate includes forming a first insulation layer on the substrate, forming a first conductive layer on the first insulation layer, and performing two separate etches to form first and second trenches through the first conductive layer. A sidewall of the first conductive layer at the first trench has a negative slope and a sidewall of the first conductive layer at the second trench is vertical.

First claim

What is claimed is:

1. A method of forming a memory device, comprising:
forming, in a substrate of a first conductivity type, spaced apart first and second regions of a second conductivity type, defining a channel region therebetween;
forming a floating gate disposed over and insulated from a first portion of the channel region which is adjacent the first region;
forming a control gate disposed over and insulated from the floating gate;
forming an erase gate disposed over and insulated from the first region;
forming a select gate over and insulated from a second portion of the channel region which is adjacent to the second region;
wherein the forming of the floating gate includes:
forming a first insulation layer on the substrate,
forming a first conductive layer on the first insulation layer,
performing a first etch to form a first trench through the first conductive layer, and
performing a second etch different than the first etch to form a second trench through the first conductive layer,
wherein the floating gate constitutes the first conductive layer between the first and second trenches,
wherein the first region is disposed under the first trench,
wherein a sidewall of the first conductive layer at the first trench has a negative slope, and wherein a sidewall of the first conductive layer at the second trench is vertical.

2. The method of claim 1 , wherein the forming of the select gate includes depositing a polysilicon layer over and insulated from the substrate, and etching through the polysilicon layer leaving a first block of the polysilicon layer laterally adjacent to and insulated from the floating gate and the control gate.

3. The method of claim 2 , further comprising forming a first logic device on the substrate by:
forming a first logic gate over and insulated from the substrate;
forming in the substrate spaced apart third and fourth regions of the second conductivity type, defining a second channel region therebetween;
wherein the first logic gate is disposed over the second channel region and is formed by:
etching through the polysilicon layer leaving a second block of the polysilicon layer,
removing and replacing the second block of the polysilicon layer with a first block of metal material that constitutes the first logic gate.

4. The method of claim 3 , further comprising forming a second logic device on the substrate by:
forming a second logic gate over and insulated from the substrate;
forming in the substrate spaced apart fifth and sixth regions of the second conductivity type, defining a third channel region therebetween;
wherein the second logic gate is disposed over the third channel region and is formed by
etching through the polysilicon layer leaving a third block of the polysilicon layer;
removing and replacing the third block of the polysilicon layer with a second block of metal material that constitutes the second logic gate.

5. The method of claim 4 , wherein:
the first logic gate is insulated from the substrate by a second insulation layer;
the second logic gate is insulated from the substrate by a third insulation layer;
the second insulation layer is thicker than the third insulation layer.

6. The method of claim 4 , wherein the first and second logic gates each have a height lower than a height of select gate.

7. A method of forming a memory device, comprising:
forming, in a substrate of a first conductivity type, spaced apart first and second regions of a second conductivity type, defining a channel region therebetween;
forming a floating gate disposed over and insulated from a first portion of the channel region which is adjacent the first region;
forming a control gate disposed over and insulated from the floating gate;
forming an erase gate disposed over and insulated from the first region;
forming a select gate over and insulated from a second portion of the channel region which is adjacent to the second region;
wherein the forming of the floating gate includes depositing a first polysilicon layer over and insulated from the substrate, and etching through the first polysilicon layer leaving a block of the first polysilicon layer that constitutes the floating gate;
wherein the forming of the control gate includes depositing a second polysilicon layer over and insulated from the first polysilicon layer, and etching through the second polysilicon layer leaving a block of the second polysilicon layer that constitutes the control gate;
wherein the forming of the erase gate includes depositing a third polysilicon layer over and insulated from the first region;
wherein the forming of the select gate includes depositing a fourth polysilicon layer over and insulated from the substrate, and etching through the fourth polysilicon layer leaving a first block of the fourth polysilicon layer laterally adjacent to and insulated from the floating gate and the control gate.

8. The method of claim 7 , wherein the first block of the fourth polysilicon layer constitutes the select gate.

9. The method of claim 7 , wherein the forming of the select gate further comprises:
removing and replacing the first block of the fourth polysilicon layer with a first block of metal material which constitutes the select gate.

10. The method of claim 7 , further comprising forming a first logic device on the substrate by:
forming a first logic gate over and insulated from the substrate;
forming in the substrate spaced apart third and fourth regions of the second conductivity type, defining a second channel region therebetween;
wherein the first logic gate is disposed over the second channel region and is formed by:
etching through the fourth polysilicon layer leaving a second block of the fourth polysilicon layer,
removing and replacing the second block of the fourth polysilicon layer with a first block of metal material that constitutes the first logic gate.

11. The method of claim 10 , further comprising forming a second logic device on the substrate by:
forming a second logic gate over and insulated from the substrate;
forming in the substrate spaced apart fifth and sixth regions of the second conductivity type, defining a third channel region therebetween;
wherein the second logic gate is disposed over the third channel region and is formed by:
etching through the fourth polysilicon layer leaving a third block of the fourth polysilicon layer,
removing and replacing the third block of the fourth polysilicon layer with a second block of metal material that constitutes the second logic gate.

12. The method of claim 11 , wherein:
the first logic gate is insulated from the substrate by a first insulation layer;
the second logic gate is insulated from the substrate by a second insulation layer;
the first insulation layer is thicker than the second insulation layer.

13. The method of claim 11 , wherein the first and second logic gates each have a height lower than a height of select gate.

Assignees

• Silicon Storage Tech Inc

Inventors

• Yang Jeng-Wei
• Chen Chun-Ming
• Wu Man-Tang
• Zhou Feng
• Liu Xian
• Su Chien-Sheng
• Do Nhan

Classifications

• H10P50/642

  Chemical etching · CPC title

• H01L21/30604

  Electricity · mapped topic

• H01L27/11524 Primary

  Electricity · mapped topic

• H01L27/11536

  Electricity · mapped topic

• H01L21/28273

  Electricity · mapped topic