Method of forming memory array and logic devices

Patent metadata

Field	Value
Publication number	US-9673208-B2
Application number	US-201615264457-A
Country	US
Kind code	B2
Filing date	Sep 13, 2016
Priority date	Oct 12, 2015
Publication date	Jun 6, 2017
Grant date	Jun 6, 2017

Abstract

A method of forming a memory device on a substrate having memory, core and HV device areas. The method includes forming a pair of conductive layers in all three areas, forming an insulation layer over the conductive layers in all three areas (to protect the core and HV device areas), and then etching through the insulation layer and the pair of conductive layers in the memory area to form memory stacks. The method further includes forming an insulation layer over the memory stacks (to protect the memory area), removing the pair of conductive layers in the core and HV device areas, and forming conductive gates disposed over and insulated from the substrate in the core and HV device areas.

First claim

What is claimed is:

1. A method of forming a memory device, comprising:
providing a semiconductor substrate having a memory array area, a core device area and an HV device area;
forming a first conductive layer over and insulated from the substrate in the memory array, core device, and HV device areas;
forming a second conductive layer over and insulated from the first conductive layer in the memory array, core device, and HV device areas;
forming a first insulation layer over the second conductive layer in the memory array, core device, and HV device areas;
etching through portions of the first insulation layer and the first and second conductive layers in the memory array area to form pairs of stacks, wherein each of the stacks includes a block of the second conductive layer over and insulated from a block of the first conductive layer;
forming source regions in the substrate, wherein each of the source regions is disposed between the stacks of one of the pairs of stacks;
forming a third conductive layer in the memory array, core device and HV device areas;
removing the third conductive layer from the core device and HV device areas;
forming a second insulation layer over the third conductive layer in the memory array area and over the first insulation layer in the core device and HV device areas;
removing the first and second insulation layers, and the first and second conductive layers, from the core device and HV device areas;
forming conductive gates disposed over and insulated from the substrate in the core device and HV device areas;
removing the second insulation layer in the memory array area;
removing portions of the third conductive layer to form blocks of the third conductive layer adjacent to and insulated from the pairs of stacks;
forming drain regions in the substrate adjacent the blocks of the third conductive layer in the memory array area; and
forming second source and second drain regions in the substrate adjacent the conductive gates in the core device and HV device areas.

2. The method of claim 1 , wherein the first insulation layer is oxide, nitride or a composite of oxide and nitride.

3. The method of claim 1 , wherein the second insulation layer is oxide, nitride or a composite of oxide and nitride.

4. The method of claim 1 , wherein the first, second and third conductive layers are polysilicon.

5. The method of claim 1 , wherein the conductive gates are polysilicon.

6. The method of claim 1 , wherein the conductive gates are metal.

7. The method of claim 6 , wherein the conductive gates are insulated from the substrate by a high K material.

8. The method of claim 1 , wherein the removing the third conductive layer from the core device and HV device areas further comprises:
removing a top portion of the third conductive layer from the memory array area, resulting in a plurality of blocks of the third conductive layer each disposed between the stacks of one of the pairs of stacks.

9. The method of claim 1 , wherein insulation between the conductive gates and the substrate in the HV device area is thicker than insulation between the conductive gates and the substrate in the core device area.

10. The method of claim 1 , wherein the forming of the conductive gates further comprises:
forming a third insulation layer directly on the substrate in the core device and HV device areas;
removing the third insulation layer in the core device area and
forming a fourth insulation layer directly on the substrate in the core device area;
forming the conductive gates directly on the third insulation layer in the HV device area and directly on the fourth insulation layer in the core device area;
wherein the third insulation layer is thicker than the fourth insulation layer.

11. A method of forming a memory device, comprising:
providing a semiconductor substrate having a memory array area, a core device area and an HV device area;
forming a first conductive layer over and insulated from the substrate in the memory array, core device, and HV device areas;
forming a second conductive layer over and insulated from the first conductive layer in the memory array, core device, and HV device areas;
forming a first insulation layer over the second conductive layer in the memory array, core device, and HV device areas;
etching through portions of the first insulation layer and the first and second conductive layers in the memory array area to form pairs of stacks, wherein each of the stacks includes a block of the second conductive layer over and insulated from a block of the first conductive layer;
forming source regions in the substrate, wherein each of the source regions is disposed between the stacks of one of the pairs of stacks;
forming a third conductive layer in the memory array, core device and HV device areas;
removing the third conductive layer from the core device and HV device areas;
forming a second insulation layer over the third conductive layer in the memory array area and over the first insulation layer in the core device and HV device areas;
removing the first and second insulation layers, and the first and second conductive layers, from the core device and HV device areas;
forming a fourth conductive layer disposed over and insulated from the substrate in the core device and HV device areas;
removing the second insulation layer in the memory array area;
removing portions of the third conductive layer to form blocks of the third conductive layer adjacent to and insulated from the pairs of stacks;
removing portions of the fourth conductive layer to form conductive gates disposed over and insulated from the substrate in the core device and HV device areas;
forming drain regions in the substrate adjacent the blocks of the third conductive layer in the memory array area; and
forming second source and second drain regions in the substrate adjacent the conductive gates in the core device and HV device areas.

12. The method of claim 11 , wherein the first insulation layer is oxide, nitride or a composite of oxide and nitride.

13. The method of claim 11 , wherein the second insulation layer is oxide, nitride or a composite of oxide and nitride.

14. The method of claim 11 , wherein the first, second and third conductive layers are polysilicon.

15. The method of claim 11 , wherein the fourth conductive layer is polysilicon.

16. The method of claim 11 , wherein the fourth conductive layer is metal.

17. The method of claim 16 , wherein the fourth conductive layer is insulated from the substrate by a high K material.

18. The method of claim 11 , wherein the removing the third conductive layer from the core device and HV device areas further comprises:
removing a top portion of the third conductive layer from the memory array area, resulting in a plurality of blocks of the third conductive each disposed between the stacks of one of the pairs of stacks.

19. The method of claim 11 , wherein insulation between the conductive gates and the substrate in the HV device area is thicker than insulation between the conductive gates and the substrate in the core device area.

20. The method of claim 11 , wherein the forming of the conductive gates further comprises:
forming a third insulation layer directly on the substrate in the core device and HV device areas;
removing the third insulation layer in the core device area and
forming a fourth insulation layer directly on the substrate in the core device area;
forming the fourth conductive layer directly on the third i

Assignees

• Silicon Storage Tech Inc

Inventors

• Kim Jinho
• Su Chien-Sheng
• Zhou Feng
• Liu Xian
• Do Nhan
• Tuntasood Prateep
• Ghazavi Parviz

Classifications

• H01L27/11531 Primary

  Electricity · mapped topic

• H10D30/6892 Primary

  having at least one additional gate other than the floating gate and the control gate, e.g. program gate, erase gate or select gate · CPC title

• H10B41/47

  with a floating-gate layer also being used as part of the peripheral transistor · CPC title

• H10B41/46

  with an inter-gate dielectric layer also being used as part of the peripheral transistor · CPC title

• H10B41/44

  with a control gate layer also being used as part of the peripheral transistor · CPC title