Electronic chip manufacturing method

Patent metadata

Field	Value
Publication number	US-2017200730-A1
Application number	US-201615228236-A
Country	US
Kind code	A1
Filing date	Aug 4, 2016
Priority date	Jan 12, 2016
Publication date	Jul 13, 2017
Grant date	—

Abstract

Active areas of memory cells and active areas of transistors are delimited in an upper portion of a wafer. Floating gates are formed on active areas of the memory cells. A silicon oxide-nitride-oxide tri-layer is then deposited over the wafer and a protection layer is deposited over the silicon oxide-nitride-oxide tri-layer. Portions of the protection layer and tri-layer located over the active areas of transistors are removed. Dielectric layers are formed over the wafer and selectively removed from covering the non-removed portions of the protection layer and tri-layer. A memory cell gate is then formed over the non-removed portions of the protection layer and tri-layer and a transistor gate is then formed over the non-removed portions of the dielectric layers.

First claim

1 . An electronic chip manufacturing method, comprising the steps of:
a) delimiting a first active area for a memory cell and a second active area for a transistors in an upper portion of a wafer; b) forming a floating gate on the first active area for the memory cell; c) depositing a silicon oxide-nitride-oxide tri-layer on the wafer; d) depositing a protection layer on the wafer; e) removing a portions of the protection layer and a portion of the tri-layer located on a portion of the wafer where the second active area is located; f) forming dielectric layers on the wafer; and g) removing a portion of said dielectric layers which covers a non-removed portion of the protection layer.

2 . The method of claim 1 , wherein step f) comprises the steps of:
f1) forming a first silicon oxide layer over the wafer; and f2) forming a second layer of a material of high permittivity.

3 . The method of claim 2 , wherein the second layer is a stack of layers comprising a hafnium silicate layer topping a silicon oxynitride layer.

4 . The method of claim 2 , wherein the second layer has a thickness in a range from 1.5 to 3 nm.

5 . The method of claim 2 , wherein said second active area comprises a first sub-active area for first transistors and a second sub-active area for second transistors, further comprising, between steps f1) and f2), the steps of:
removing portions of the first silicon oxide layer covering the first sub-active area for the first transistors; and thermally oxidizing a surface to form an oxide layer in an upper portion of the first sub-active areas for the first transistors.

6 . The method of claim 1 , further comprising, between steps f) and g), a step of depositing a metal layer on the dielectric layers, followed by a step of removing portions of the metal layer located above non-removed portions of the protection layer.

7 . The method of claim 1 , comprising, after step g), a step of removing a remainder of the protection layer.

8 . The method of claim 1 , wherein the protection layer has a thickness in a range from 3 to 500 nm.

9 . The method of claim 1 , wherein the protection layer is made of amorphous silicon.

10 . The method of claim 1 , wherein the protection layer is made of polysilicon.

11 . An electronic chip, comprising:
a memory cell and a transistor supported by a substrate; of a silicon oxide-nitride-oxide tri-layer arranged on a floating gate of said memory cell; and a material of high permittivity arranged over an active area of said transistor.

12 . A method, comprising the following steps performed in sequence:
delimiting a first active area and a second active area of a substrate; forming a floating gate electrode over the first active area; depositing a silicon oxide-nitride-oxide tri-layer over the floating gate electrode and over the second active area; depositing a protection layer over the silicon oxide-nitride-oxide tri-layer; removing the protection layer and silicon oxide-nitride-oxide tri-layer from over the second active area; forming one or more dielectric layers over a remaining portion of the protection layer and over the second active area; removing the one or more dielectric layers from over the remaining portion of the protection layer; removing the remaining portion of the protection layer; forming a first gate electrode over a remaining portion of the silicon oxide-nitride-oxide tri-layer and the floating gate electrode; and forming a second gate electrode over the a remaining portion of the one or more dielectric layers and the second active area.

13 . The method of claim 12 , wherein forming one or more dielectric layers comprises:
forming a silicon oxide layer; and forming a layer of a material of high permittivity on said silicon oxide layer.

14 . The method of claim 13 , wherein the second layer is a stack of layers comprising a hafnium silicate layer topping a silicon oxynitride layer.

15 . The method of claim 13 , wherein the second layer has a thickness in a range from 1.5 to 3 nm.

16 . The method of claim 12 , wherein forming one or more dielectric layers comprises:
thermally oxidizing a surface of the second active area of the substrate to form an oxide layer; and forming a layer of a material of high permittivity on said silicon oxide layer.

17 . The method of claim 16 , wherein the second layer is a stack of layers comprising a hafnium silicate layer topping a silicon oxynitride layer.

18 . The method of claim 16 , wherein the second layer has a thickness in a range from 1.5 to 3 nm.

19 . The method of claim 12 , wherein the protection layer is made of amorphous silicon.

20 . The method of claim 21 , wherein the protection layer is made of polysilicon.

Assignees

• St Microelectronics Crolles 2 Sas

Inventors

• Zoll Stephane
• Garnier Philippe

Classifications

• H01L21/28282

  Electricity · mapped topic

• H01L21/28273

  Electricity · mapped topic

• H01L27/11539 Primary

  Electricity · mapped topic

• H01L27/11521

  Electricity · mapped topic

• H01L29/7887

  Electricity · mapped topic