NoC timing power estimating device and method thereof
US-9842180-B2 · Dec 12, 2017 · US
System on chip [SoC] design
System on chip [SoC] design · Cooperative Patent Classification (CPC)
Computing, optics, measurement, and control technologies.
Related technology areas
Mapped technology topics for this CPC code.
| Metric | Value |
|---|---|
| CPC code | G06F2115/02 |
| Official title | System on chip [SoC] design |
| Display label | System on chip [SoC] design |
| Total patents | 455 |
Filing trend
Year-over-year patent counts classified under this CPC code.
Filing activity over the last five years is stable.
| Year | Patents |
|---|---|
| 2015 | 14 |
| 2016 | 17 |
| 2017 | 42 |
| 2018 | 25 |
| 2019 | 29 |
| 2020 | 41 |
| 2021 | 43 |
| 2022 | 48 |
| 2023 | 58 |
| 2024 | 67 |
| 2025 | 51 |
| 2026 | 20 |
Representative patents
Representative publications under this CPC code from precomputed stats, or recent filings when stats are unavailable.
Method and system for generating post-silicon validation tests
US-9823305-B1 · Nov 21, 2017 · US
Estimation of chip floorplan activity distribution
US-2017316145-A1 · Nov 2, 2017 · US
Method and system for debugging a system on chip under test
US-9792402-B1 · Oct 17, 2017 · US
Verification low power collateral generation
US-9785732-B2 · Oct 10, 2017 · US
Computer implemented system and method for modifying a layout of standard cells defining a circuit component
US-9785740-B2 · Oct 10, 2017 · US
Automating system on a chip customized design integration, specification, and verification through a single, integrated service
US-9760668-B2 · Sep 12, 2017 · US
Intra-run design decision process for circuit synthesis
US-9703920-B2 · Jul 11, 2017 · US
Safety features for high level design
US-9690894-B1 · Jun 27, 2017 · US
Intra-run design decision process for circuit synthesis
US-9690900-B2 · Jun 27, 2017 · US
Computer Implemented System and Method for Modifying a Layout of Standard Cells Defining a Circuit Component
US-2017177785-A1 · Jun 22, 2017 · US
EDITING A NoC TOPOLOGY ON TOP OF A FLOORPLAN
US-2017177778-A1 · Jun 22, 2017 · US
Automating system on a chip customized design integration, specification, and verification through a single, integrated service
US-9684752-B2 · Jun 20, 2017 · US
Method of component partitions on system on chip and device thereof
US-2017161420-A1 · Jun 8, 2017 · US
System-on-chip intellectual property block discovery
US-9639646-B2 · May 2, 2017 · US
Automating system on a chip customized design integration, specification, and verification through a single, integrated service
US-2017116355-A1 · Apr 27, 2017 · US
Layout design system, method, and semiconductor device employing termination-free unit designs
US-9633161-B2 · Apr 25, 2017 · US
Common template for electronic article
US-9613174-B2 · Apr 4, 2017 · US
Rectilinear macros having non-uniform channel spacing
US-2017091365-A1 · Mar 30, 2017 · US
Automating system on a chip customized design integration, specification, and verification through a single, integrated service
US-9589089-B2 · Mar 7, 2017 · US
Frequently asked questions
Answers are generated from the same data shown on this page.
- What is CPC G06F2115/02?
- CPC G06F2115/02 is the Cooperative Patent Classification code for “System on chip [SoC] design.”
- How many patents are filed under CPC G06F2115/02 (System on chip [SoC] design)?
- Our database includes 455 publications tagged with this CPC code.
- Is patent activity under CPC G06F2115/02 growing?
- Publication counts under this code: 67 in 2024 vs 51 in 2025 (latest complete years).