Layout design system, method, and semiconductor device employing termination-free unit designs

Patent metadata

Field	Value
Publication number	US-9633161-B2
Application number	US-201414474484-A
Country	US
Kind code	B2
Filing date	Sep 2, 2014
Priority date	Nov 18, 2013
Publication date	Apr 25, 2017
Grant date	Apr 25, 2017

Abstract

A layout design system includes a processor; a storage unit configured to store a first unit design having a first area, wherein in the first unit design, a termination is not placed on a border thereof; and a design module configured to generate a second unit design having a second area larger than the first area by placing the termination on a border of the first unit.

First claim

What is claimed is:

1. A semiconductor design system, comprising:
a processor and memory configured as:
a layout module to supply termination-free unit designs, each having a plurality of sides, wherein the layout module is configured to combine a plurality of termination-free unit designs in a layout;
an outline setting module to set an outline on borders of each termination-free unit design in the layout; and
a termination generation module to establish terminations for the unit designs within the respective borders of the unit designs, wherein the terminations are not included on all sides of a unit design and border areas associated with a termination-free side of the unit design may be employed for placement of a neighboring unit design.

2. The semiconductor design system of claim 1 , wherein the termination-free unit design is a cell level design.

3. The semiconductor design system of claim 1 , wherein the termination-free unit design is a macro-level design.

4. The semiconductor design system of claim 1 , wherein the terminations includes at least one of a dummy gate electrode and a dummy active fin.

5. The semiconductor design system of claim 4 , wherein the terminations includes a first termination including the dummy gate electrode and the second termination including a dummy active fin,
the first termination is placed to extend in a first direction along the border of a termination-free unit design, and
the second termination is placed to extend in a second direction crossing the first direction along the border of a combination of the termination-free unit designs.

6. The semiconductor design system of claim 5 , wherein the first termination includes the plurality of dummy gate electrodes, and
the second termination includes the plurality of dummy active fins.

7. The semiconductor design system of claim 1 , wherein:
the layout module is configured to place the termination-free unit designs;
the outline setting module is configured to set an outline around the placed termination-free unit designs; and
the termination generation module is configured to generate a termination within the border.

8. The semiconductor design system of claim 1 , wherein a termination-free unit design is stored in the memory or in another separate memory.

9. The semiconductor design system of claim 1 , wherein a termination-free unit design includes an inverter design, and
a combined termination-free unit design includes a logic block design.

10. The semiconductor design system of claim 1 , wherein a termination-free unit design includes a memory cell design, and
a combined termination-free unit design includes a memory cell array design.

Assignees

• Samsung Electronics Co Ltd

Inventors

• Baek Sang-Hoon
• Oh Sang-Kyu
• Ha Na-Ya
• Paek Seung-Weon
• Song Tae-Joong

Classifications

• G06F30/39

  Circuit design at the physical level (physical level design for reconfigurable circuits G06F30/347) · CPC title

• G06F30/392 Primary

  Floor-planning or layout, e.g. partitioning or placement · CPC title

• H10D84/853

  comprising FinFETs · CPC title

• H01L27/1104

  Electricity · mapped topic

• H01L27/0924

  Electricity · mapped topic