Computer implemented system and method for modifying a layout of standard cells defining a circuit component

Patent metadata

Field	Value
Publication number	US-9785740-B2
Application number	US-201514975482-A
Country	US
Kind code	B2
Filing date	Dec 18, 2015
Priority date	Dec 18, 2015
Publication date	Oct 10, 2017
Grant date	Oct 10, 2017

Abstract

A computer implemented system and method is provided for modifying a layout of one or more standard cells defining a circuit component, the layout providing a layout pattern for a process technology. The method comprises receiving, after completion of one or more initial place and route operations, an input data file that includes the layout pattern of the layout. The layout includes the one or more standard cells and placement and routing information generated by the one or more initial place and route operations. The method further comprises identifying one or more metal portions associated with one or more rails of the one or more standard cells of the layout. A metal fill operation is then performed using the input data file in order to generate a modified input data file. The metal fill operation includes modifying the one or more metal portions with one or more metal fill patterns to form a reduced resistive path associated with the one or more metal portions.

First claim

The invention claimed is:

1. A computer implemented method comprising:
receiving, after completion of one or more initial place and route operations, an input data file that includes a layout of one or more standard cells for a process technology, wherein the layout includes placement and routing information generated by the one or more initial place and route operations;
identifying one or more metal portions in the one or more standard cells, the one or more metal portions associated with one or more rails of the one or more standard cells of the layout;
performing a metal fill operation on the input data file in order to generate a modified input data file, wherein the metal fill operation includes modifying the one or more metal portions with one or more metal fill patterns to form a reduced resistive path associated with the one or more metal portions;
modifying the layout of the one or more standard cells utilizing the modified input data file;
generating, from an input functional definition of an integrated circuit, a layout design incorporating the modified layout of the one or more standard cells; and
manufacturing the integrated circuit from the layout design.

2. The method of claim 1 , wherein the metal portions include rail portions, strap portions, or both.

3. The method of claim 1 , wherein the one or more metal fill patterns are metal-2 layer patterns.

4. The method of claim 1 , wherein the layout is associated with a system on a chip (SoC).

5. The method of claim 1 , wherein the process technology is associated with a double patterning technique.

6. The method of claim 1 , wherein a process size of the process technology is less than or equal to 16 nm.

7. The method of claim 1 , wherein the process technology is associated with nonplanar multi-gate devices.

8. The method of claim 1 , wherein the one or more rails includes a power rail, a ground rail, or both.

9. The method of claim 1 , wherein the one or more standard cells include power switching cells.

10. The method of claim 1 , wherein modifying the one or more metal portions includes:
adding the one or more metal fill patterns to the layout, wherein the added one or more metal fill patterns substantially contact the one or more metal portions; and
removing the added one or more metal fill patterns that do not satisfy one or more conditions associated with the process technology.

11. The method of claim 10 , wherein adding the one or more metal fill patterns further includes placing the one or more metal fill patterns along the entire length of the one or more metal portions.

12. The method of claim 11 , wherein the added one or more metal fill patterns have a minimum width of the process technology.

13. The method of claim 10 , wherein the one or more conditions include one or more design rule check (DRC) conditions, one or more pin access conditions, or both.

14. The method of claim 10 , wherein the contact provides a substantial electrical connection between the added one or more metal fill patterns and the one or more metal portions.

15. The method of claim 1 , further comprising performing one or more place and route operations and one or more metal correction operations on the modified input data file in order to form an output data file providing a layout pattern of the one or more modified metal portions.

16. The method of claim 1 , further comprising merging a layout pattern of the one or more modified metal portions into drawn metal associated with the process technology.

17. The method of claim 16 , wherein the drawn metal is logically connected to one or more power supply networks associated with the layout.

18. A computer program product on a non-transitory storage medium for controlling a computer to perform the method of claim 1 .

19. A system, comprising:
means for receiving, after completion of one or more initial place and route operations, an input data file that includes a layout of one or more standard cells for a process technology, wherein the layout includes placement and routing information generated by the one or more initial place and route operations;
means for identifying one or more metal portions in the one or more standard cells, the one or more metal portions associated with one or more rails of the one or more standard cells of the layout;
means for performing a metal fill operation on the input data file in order to generate a modified input data file, wherein the metal fill operation includes modifying the one or more metal portions with one or more metal fill patterns to form a reduced resistive path associated with the one or more metal portions;
means for modifying the layout of the one or more standard cells utilizing the modified input data file;
means for generating, from an input functional definition of an integrated circuit, a layout design incorporating the modified layout of the one or more standard cells; and
manufacturing the integrated circuit from the layout design.

Assignees

• Advanced Risc Mach Ltd

Inventors

• Lowe Ivan Michael

Classifications

• G06F30/30

  Circuit design · CPC title

• G06F30/39

  Circuit design at the physical level (physical level design for reconfigurable circuits G06F30/347) · CPC title

• G06F30/392

  Floor-planning or layout, e.g. partitioning or placement · CPC title

• G06F30/398 Primary

  Design verification or optimisation, e.g. using design rule check [DRC], layout versus schematics [LVS] or finite element methods [FEM] (optical proximity correction [OPC] design processes G03F1/36) · CPC title

• G06F30/394

  Routing (G06F30/396 takes precedence) · CPC title