Safety features for high level design

Patent metadata

Field	Value
Publication number	US-9690894-B1
Application number	US-201514930407-A
Country	US
Kind code	B1
Filing date	Nov 2, 2015
Priority date	Nov 2, 2015
Publication date	Jun 27, 2017
Grant date	Jun 27, 2017

Abstract

This disclosure relates generally to electronic design automation using high level synthesis techniques to generate circuit designs that include safety features. The algorithmic description representation can be specified in a first language and include at least one programming language construct associated with a first safety data type. Compiling the algorithmic description may involve identifying the at least one construct, accessing a first safety data type definition associated with the first safety data type, and generating a second representation of the circuit design based on the algorithmic description representation and the first safety data type definition. The second representation can be provided in a second language and include at least one safety feature for a portion of the circuit design associated with the at least one construct.

First claim

What is claimed is:

1. One or more tangible computer-readable media at least collectively storing a non-transitory code executable by one or more processors, the code being configured to, when executed by the one or more processors, cause operations to be performed including:
accessing an algorithmic description representation of a circuit design, the algorithmic description representation being specified in a first language and including at least one programming language construct associated with a first safety data type; and
compiling the algorithmic description representation of the circuit design, the compiling including:
identifying the at least one programming language construct,
accessing a first safety data type definition associated with the first safety data type, and
generating a second representation of the circuit design based on the algorithmic description representation and the first safety data type definition, the second representation being provided in a second language and including at least one safety feature for a portion of the circuit design associated with the at least one programming language construct.

2. The media of claim 1 , wherein the algorithmic description representation is a control-flow-based representation and wherein the second representation is a data-flow-based representation.

3. The media of claim 1 , wherein the first language is an OpenCL-compatible programming language.

4. The media of claim 1 , wherein the second representation of the circuit design is a register-transfer level (RTL) representation.

5. The media of claim 1 , wherein the algorithmic description representation includes one or more directives identifying one or more header files, the one or more header files defining one or more safety data types including the first safety data type.

6. The media of claim 5 , wherein the compiling further includes:
identifying the one or more directives;
identifying the one or more header files;
accessing the one or more header files;
retrieving contents of the one or more header files; and
including the contents of the one or more header files in the algorithmic description representation prior to generating the second representation.

7. The media of claim 1 , wherein the at least one programming language construct includes at least one variable defined using the first safety data type.

8. The media of claim 1 , wherein the at least one programming language construct includes at least one function having a return type defined using the first safety data type.

9. The media of claim 1 , wherein the at least one programming language construct includes at least one function including at least one parameter defined using the first safety data type.

10. The media of claim 1 , wherein the at least one programming language construct includes at least one pragma directive identifying a function as a safety-critical function.

11. A system comprising:
one or more memory devices at least collectively storing a non-transitory processor-executable code configured to implement instructions;
one or more processing devices to execute the processor-executable code to implement the instructions, the instructions configured to cause operations to be performed including:
accessing an algorithmic description representation of a circuit design, the algorithmic description representation being specified in a first language and including at least one programming language construct associated with a first safety data type; and
compiling the algorithmic description representation of the circuit design, the compiling including:
identifying the at least one programming language construct,
accessing a first safety data type definition associated with the first safety data type, and
generating a second representation of the circuit design based on the algorithmic description representation and the first safety data type definition, the second representation being provided in a second language and including at least one safety feature for a portion of the circuit design associated with the at least one programming language construct.

12. The system of claim 11 , wherein the algorithmic description representation is a control-flow-based representation and wherein the second representation is a data-flow-based representation.

13. The system of claim 11 , wherein the algorithmic description representation includes one or more directives identifying one or more header files, the one or more header files defining one or more safety data types including the first safety data type.

14. The system of claim 13 , wherein the compiling further includes:
identifying the one or more directives;
identifying the one or more header files;
accessing the one or more header files;
retrieving contents of the one or more header files; and
including the contents of the one or more header files in the algorithmic description representation prior to generating the second representation.

15. The system of claim 11 , wherein the at least one programming language construct includes at least one variable defined using the first safety data type.

16. The system of claim 11 , wherein the at least one programming language construct includes at least one function having a return type defined using the first safety data type.

17. The system of claim 11 , wherein the at least one programming language construct includes at least one function including at least one parameter defined using the first safety data type.

18. The system of claim 11 , wherein the at least one programming language construct includes at least one pragma directive identifying a function as a safety-critical function.

19. A method comprising:
accessing, by a computer system, an algorithmic description representation of a circuit design, the algorithmic description representation being specified in a first language and including at least one programming language construct associated with a first safety data type; and
compiling, by the computer system, the algorithmic description representation of the circuit design, the compiling including:
identifying the at least one programming language construct,
accessing a first safety data type definition associated with the first safety data type, and
generating a second representation of the circuit design based on the algorithmic description representation and the first safety data type definition, the second representation being provided in a second language and including at least one safety feature for a portion of the circuit design associated with the at least one programming language construct.

20. The method of claim 19 , wherein the algorithmic description representation is a control-flow-based representation and wherein the second representation is a data-flow-based representation.

Assignees

• Altera Corp

Inventors

• Titley Adam

Classifications

• G06F30/327

  Logic synthesis; Behaviour synthesis, e.g. mapping logic, HDL to netlist, high-level language to RTL or netlist · CPC title

• G06F30/30

  Circuit design · CPC title

• G06F30/34 Primary

  for reconfigurable circuits, e.g. field programmable gate arrays [FPGA] or programmable logic devices [PLD] · CPC title

• G06F17/505

  Physics · mapped topic

• G06F17/5054

  Physics · mapped topic